Saturday, September 14
ESD Compliance Verification Technician to TR53 - Day 1
Chuck McClain
Andrew Nold
Andy Nold is a Quality Engineer and Commodity Engineer at Teradyne near Chicago, IL. He is the Factory ESD subject matter expert and performs the company’s internal ESD audits. He has worked for Teradyne since 2011.
Prior to Teradyne, Andy worked for the FAA, a small aerospace company, and the US Navy. Andy graduated from the University of Wisconsin with a bachelor’s degree in Applied Math, Engineering, and Physics and a master’s degree in Engineering Mechanics.
Outside of work, Andy likes to spend time with his wife and kids.
ESD Compliance Verification Technician to TR53 - Day 1
FC100: ESD Basics for the Program Manager
Jay Skolnik
Jay Skolnik is a licensed professional electrical engineer and is the co-founder and lead engineer/consultant of Skolnik Technical Training in Albuquerque, NM. With over thirty years of experience in the electronics industry, Jay has developed a multitude of products utilized in different industries, including military, defense, avionics, aerospace, commercial, industrial, medical, automotive, and sports entertainment.
As an ESDA certified program manager, Jay teaches ESD mitigation and control for the electronics and energetics specialties. He performs ESD audits to ensure factories and laboratories are following safe ESD control guidelines and procedures. He is also certified by iNARTE and is a certified professional instructor of national instruments (NI). He received his electrical engineering degree from the University of Missouri-Rolla.
FC100: ESD Basics for the Program Manager
FC340: ESD Program Development and Assessment (ANSI/ESD S20.20 Seminar) - Day 1
David Swenson
David E. Swenson retired in 2003 after 35 years of service from 3M. While at 3M he had responsibility for new packaging material development and application, training of 3M personnel worldwide and providing application assistance to users of static control products globally with particular emphasis on Asia Pacific and Japan. Dave and his wife Geri established a new company, Affinity Static Control Consulting, LLC. in 2003.
Dave has been a member of the ESD Association since 1984 and has served in many capacities including 1997 Symposium General Chair and president of the Association in 1998 and 1999 and again in 2008 and 2009. He was re-elected to the Board of Directors for a 5th term from 2014 to 2016 and is currently appointed to the Board to assist with technical inquiries.
Dave was presented with the highest award of the ESD Association, the “Outstanding Contributions Award” in 2002, the Standards Committee “Joel P. Weidendorf Memorial Award” in 2004, the Association “Edward G. Weggeland” Memorial Award in 2014 and the Symposium Committee’s, David Barber, Sr. Memorial award in 2018.
He is a member of the Standards Committee serving several Working Groups and the ANSI/ESD S20.20 Standard Task Team. Dave also serves as Treasurer and Information Liaison of the Texas Chapter of the ESD Association; he is a member of the Electrostatic Society of America, IMAPS, the UK Institute of Physics and is a US Expert to IEC TC101, Electrostatics.
FC340: ESD Program Development and Assessment (ANSI/ESD S20.20 Seminar) - Day 1
Introduction to On-Chip ESD Protection
Oliver Marichal
Olivier Marichal graduated from Katholieke Universiteit Leuven with a degree in Electrical Engineering in 2003 and has since dedicated his career to the field of Electrostatic Discharge (ESD) protection design, currently serving as Chief Engineering at Sofics. His journey with the company began shortly after graduation as an ESD engineer, and over the years, Olivier has worked on many projects, covering a broad range of technologies from High Voltage BCD to the latest nanometer Finfet processes. His professional focus is on continuously adding value to customers through his work, delivering state-of-the-art ESD solutions for the ever-evolving landscape of semiconductor applications.
Olivier has (co-)authored several papers on ESD and contributed as an inventor on many patents. In addition to his technical contributions, Olivier is dedicated to sharing his knowledge and insights. He has conducted several tutorials on on-chip ESD protection design for industry professionals around the world.
Introduction to On-Chip ESD Protection
Sunday, September 15
ESD Compliance Verification Technician to TR53 - Day 2
Chuck McClain
Andrew Nold
Andy Nold is a Quality Engineer and Commodity Engineer at Teradyne near Chicago, IL. He is the Factory ESD subject matter expert and performs the company’s internal ESD audits. He has worked for Teradyne since 2011.
Prior to Teradyne, Andy worked for the FAA, a small aerospace company, and the US Navy. Andy graduated from the University of Wisconsin with a bachelor’s degree in Applied Math, Engineering, and Physics and a master’s degree in Engineering Mechanics.
Outside of work, Andy likes to spend time with his wife and kids.
ESD Compliance Verification Technician to TR53 - Day 2
FC340: ESD Program Development and Assessment (ANSI/ESD S20.20 Seminar) - Day 2
David Swenson
David E. Swenson retired in 2003 after 35 years of service from 3M. While at 3M he had responsibility for new packaging material development and application, training of 3M personnel worldwide and providing application assistance to users of static control products globally with particular emphasis on Asia Pacific and Japan. Dave and his wife Geri established a new company, Affinity Static Control Consulting, LLC. in 2003.
Dave has been a member of the ESD Association since 1984 and has served in many capacities including 1997 Symposium General Chair and president of the Association in 1998 and 1999 and again in 2008 and 2009. He was re-elected to the Board of Directors for a 5th term from 2014 to 2016 and is currently appointed to the Board to assist with technical inquiries.
Dave was presented with the highest award of the ESD Association, the “Outstanding Contributions Award” in 2002, the Standards Committee “Joel P. Weidendorf Memorial Award” in 2004, the Association “Edward G. Weggeland” Memorial Award in 2014 and the Symposium Committee’s, David Barber, Sr. Memorial award in 2018.
He is a member of the Standards Committee serving several Working Groups and the ANSI/ESD S20.20 Standard Task Team. Dave also serves as Treasurer and Information Liaison of the Texas Chapter of the ESD Association; he is a member of the Electrostatic Society of America, IMAPS, the UK Institute of Physics and is a US Expert to IEC TC101, Electrostatics.
FC340: ESD Program Development and Assessment (ANSI/ESD S20.20 Seminar) - Day 2
FC101: How To’s of In-Plant ESD Auditing and Evaluation Measurements
Jay Skolnik
Jay Skolnik is a licensed professional electrical engineer and is the co-founder and lead engineer/consultant of Skolnik Technical Training in Albuquerque, NM. With over thirty years of experience in the electronics industry, Jay has developed a multitude of products utilized in different industries, including military, defense, avionics, aerospace, commercial, industrial, medical, automotive, and sports entertainment.
As an ESDA certified program manager, Jay teaches ESD mitigation and control for the electronics and energetics specialties. He performs ESD audits to ensure factories and laboratories are following safe ESD control guidelines and procedures. He is also certified by iNARTE and is a certified professional instructor of national instruments (NI). He received his electrical engineering degree from the University of Missouri-Rolla.
FC101: How To’s of In-Plant ESD Auditing and Evaluation Measurements
Introduction to Characterization of On-Chip ESD Protection
Wim Vanhouteghem
Wim Vanhouteghem is a Senior ESD Design Engineer and the head of the measurement lab at Sofics. A 2007 graduate of KHBO (now part of the Catholic University of Leuven), Wim joined Sofics immediately after completing his studies. His work primarily focuses on ESD protection in semiconductor technologies, ranging from high-voltage BCD to FinFETs.
Wim has plenty of experience in implementing ESD protection and conducting ESD measurements. He contributed to the SEED concept and has worked on system-level ESD measurements on bare dies.
Introduction to Characterization of On-Chip ESD Protection
Overview on ESD and Latch-up Challenges in 2.5D and 3D-Stacked ICs & ESD Design Challenges of RF and High Speed I/Os
Dolphin Abessolo-Bidzo
Dr. Ir. Dolphin Abessolo-Bidzo received his M.Sc. (2004) and his Ph.D. (2007) in Electrical Engineering from ENSICAEN and from the University of Basse-Normandie, France. He is currently working as Senior Principal RF ESD & Latch-Up Design Engineer for advanced RFCMOS and BiCMOS technologies of RF and Millimeter wave applications at NXP Semiconductors.
Dolphin has published numerous articles and papers in IEEE scientific journals, symposia, and conferences on ESD, RF, and time domain analysis and holds several patents in the field of ESD protection of integrated circuits (ICs).
He is an active member of the ESDA Workgroup-18 on Electronic Design Automation (EDA) for ESD. For more than 15 years, he has regularly served in the management and the technical program committees of the International Electrostatic Discharge Workshops (IEW’s) and the EOS/ESD Symposia. Dolphin was the Management Committee General Chair of the IEW2023 in Germany and is a 2024 member of the Board of Directors.
Mirko Scholz
Dr. Mirko Scholz received his Ph.D. in Electrical Engineering from the Vrije Universiteit in Brussels (VUB) in 2013. From 2005 until 2017, he was working as an ESD researcher at imec in Leuven/Belgium. From March 2017 until June 2019, he was a program manager at the imec academy and in imec’s process technology transfer activities. Since July 2019, he has been with Infineon Technologies in Munich/Germany, where he is a Principal Engineer in ESD Development. His daily work focuses on component- and system-level ESD protection design for several RF and sensor product lines at Infineon.
Since 2007 he has been an active member of different working groups in the ESDA standards committee, currently co-chairing WG 5.6 (Human Metal Model). He was the management chair of the IEW 2018 in Belgium. Since 2019 he has been a member of the steering committee of the EOS/ESD Symposium. In this function, he is the Technical Program Committee (TPC) chair of the EOS/ESD Symposium 2023. For the 2017-2019 term and again for the 2022-2024 term, he has been an elected member of the ESDA Board of Directors. Since 2017, he has been heading the business unit of the Advanced Topics Committee of the ESDA.
He has authored/co-authored more than 100 publications, tutorials, and patents in the field of ESD design and testing. He is co-author of the 2014 Springer book “System-level ESD Protection”. He is a regular reviewer for several IEEE journals and a current member of the IRPS sub-committee on ESD and Latchup.
Overview on ESD and Latch-up Challenges in 2.5D and 3D-Stacked ICs & ESD Design Challenges of RF and High Speed I/Os
Monday, September 16
Registration Open
Registration Open
Opening Welcome
Opening Welcome
ESD Compliance Verification Technician to TR53 - Exam
Chuck McClain
Andrew Nold
Andy Nold is a Quality Engineer and Commodity Engineer at Teradyne near Chicago, IL. He is the Factory ESD subject matter expert and performs the company’s internal ESD audits. He has worked for Teradyne since 2011.
Prior to Teradyne, Andy worked for the FAA, a small aerospace company, and the US Navy. Andy graduated from the University of Wisconsin with a bachelor’s degree in Applied Math, Engineering, and Physics and a master’s degree in Engineering Mechanics.
Outside of work, Andy likes to spend time with his wife and kids.
ESD Compliance Verification Technician to TR53 - Exam
KEYNOTE: Memory Technology Advancements Driving High Performance, Reliable Systems
Chandra Mouli
Chandra Mouli is with Micron Technology Inc., Boise, ID, USA. He is currently Vice President of Device Technology R&D with responsibilities in the areas of device characterization, reliability analysis, compact models, test structure design, process & device modeling for all technologies under development in R&D. He received his undergraduate degree in Physics and MSEE from the Indian Institute of Science (IISc), Bangalore, India and Ph.D. (EE) from the University of Texas at Austin in 1994. He has previously worked at Texas Instruments Inc. He was a visiting scholar (VSRP program) at the Tata Institute of Fundamental Research (TIFR) and has been an intern at the Defense Electronics Application Lab (DEAL) in Dehra Dun. His interests include semiconductor devices and process technology for advanced memory, optoelectronic devices, and exploratory research in the area of new materials and device structures. He has ~500 issued patents and several pending in various areas of semiconductor devices and processes – in advanced memory, novel exploratory devices, image sensors, high-speed interconnects, and related technologies. He has served on the technical committees for various conferences, including IEDM, IRPS, and SISPAD. He has also served on the review committees for NSF and SRC and as an editor for IEEE Electron Device Letters (EDL).
KEYNOTE: Memory Technology Advancements Driving High Performance, Reliable Systems
Networking Break
Networking Break
Invited Talk TBA
Invited Talk TBA
Device Testing Invited Talk TBA
Kathleen Muhonen
Kathleen Muhonen is currently an ESD engineer at Qorvo in Greensboro, NC. She is involved in ESD on-chip protection for RF and Millimeter wave applications. She is heavily involved in system level testing that helps standardize IED testing of RF components and instrumentation for better ESD characterization of clamps and materials. Previously she was responsible for RF characterization and model support for SOI switches and Gallium Arsenide power amplifiers. She has also done extensive work on developing state of the art harmonic and breakdown characterization system for semiconductors and has improved de-embedding techniques of large-scale modeling structures. Kathleen's previous experience includes assistant professor at Penn State Erie, linearization design for base stations at Hewlett Packard, and power amplifier design at Lockheed Martin and GE Aerospace.
Kathleen is a member of the ESD association and is on all device testing standards committees, including serving as past TLP and HMM workgroup chairs. She has also served on the Board of Directors and is now serving as the education committee chair. Kathleen received her BSEE degree from Michigan Technological University in 91, a MSEE from Syracuse in 94 and a PH.D.EE from Penn State University in 99.
Device Testing Invited Talk TBA
Networking Coffee Break
Networking Coffee Break
1B.1 TLP/VFTLP Investigation on eNVM 1T1R PCM in FD-SOI UTBB CMOS Technology at Room Temperature (ESREF Invited Paper)
Philippe Galy
Dr. Philippe Galy, born 1965, obtained his Ph.D. from the University of Bordeaux (France) in 1994. He holds also a H.D.R. (academic research supervisor) from LAAS CNRS University of Toulouse in 2005. He has authored or co-authored over 150 publications, 4 books, and 140 patents portfolio. Philippe serves in several technical program committee and he is a reviewer for many symposiums and journals (Ex: Nature/VLSI/TED/TON/SSE/ ESREF/ESSDERC/ICICDT/EUROSOI/CAS).
He joined STMicroelectronics in 2005, working on ESD/LU and new solutions from device to SOC level in advanced CMOS and mature technologies (Bulk / FD-SOI / planar & 3D). He develops tooling concepts for robust IP integration and supervises its developments till massive production. Moreover, its main R&D topics are on SCR, T2, TFET, BIMOS transistor, Beta-structure and other innovative devices for emerging neuromorphic, Qubit applications. Philippe is in charge for STMicroelectronics on Cryogenic Quantum R&D with many international partners. Based on these topics he supervises 16 PhD. He was already involved in National & European projects ( Ex.: Nano 2017/ROBIN/REMINDER/Neuram3/ QLSI/ARCTIC). Also, he joins the QuEng CDP group from Grenoble France. Its Position today is Fellow technical Director and adjunct professor at UdS.
1B.1 TLP/VFTLP Investigation on eNVM 1T1R PCM in FD-SOI UTBB CMOS Technology at Room Temperature (ESREF Invited Paper)
Invited Talk TBA
Invited Talk TBA
1B.2 Can CC-TLP be used as an Early Failure Analysis Tool?
Chloe Troussier
Chloé Troussier received her Ph.D. degree in 2022 from University Grenoble Alpes of Grenoble, France. During her Ph.D. thesis (20018-2022), she worked on on the study of Charged Device Model phenomenon in STMicroelectronics. Since 2021, she joined STMicroelectronics Crolles as a Research Engineer working on ESD protections and strategies.
1B.2 Can CC-TLP be used as an Early Failure Analysis Tool?
Authors Corner for 1B.1 and 1B.2
Philippe Galy
Dr. Philippe Galy, born 1965, obtained his Ph.D. from the University of Bordeaux (France) in 1994. He holds also a H.D.R. (academic research supervisor) from LAAS CNRS University of Toulouse in 2005. He has authored or co-authored over 150 publications, 4 books, and 140 patents portfolio. Philippe serves in several technical program committee and he is a reviewer for many symposiums and journals (Ex: Nature/VLSI/TED/TON/SSE/ ESREF/ESSDERC/ICICDT/EUROSOI/CAS).
He joined STMicroelectronics in 2005, working on ESD/LU and new solutions from device to SOC level in advanced CMOS and mature technologies (Bulk / FD-SOI / planar & 3D). He develops tooling concepts for robust IP integration and supervises its developments till massive production. Moreover, its main R&D topics are on SCR, T2, TFET, BIMOS transistor, Beta-structure and other innovative devices for emerging neuromorphic, Qubit applications. Philippe is in charge for STMicroelectronics on Cryogenic Quantum R&D with many international partners. Based on these topics he supervises 16 PhD. He was already involved in National & European projects ( Ex.: Nano 2017/ROBIN/REMINDER/Neuram3/ QLSI/ARCTIC). Also, he joins the QuEng CDP group from Grenoble France. Its Position today is Fellow technical Director and adjunct professor at UdS.
Chloe Troussier
Chloé Troussier received her Ph.D. degree in 2022 from University Grenoble Alpes of Grenoble, France. During her Ph.D. thesis (20018-2022), she worked on on the study of Charged Device Model phenomenon in STMicroelectronics. Since 2021, she joined STMicroelectronics Crolles as a Research Engineer working on ESD protections and strategies.
Authors Corner for 1B.1 and 1B.2
Networking Break
Networking Break
Symposium Paper Awards Presentation Lunch
Symposium Paper Awards Presentation Lunch
Manufacturing Invited Talk: Air Ionization and it’s Use in Controlling Static Charge
Carl Newberg
Carl Newberg is the manager of the Applications Engineering Team at Simco-Ion Technology, an ITW Company. Simco-Ion develops ionization solutions for high-technology semiconductor, electronics, and life science manufacturing. He has a B.S. degree in Metallurgical Engineering, an M.S. Degree in Materials Science, and a professional engineer’s license (Met. Eng.). He was among the first to test and receive certification from the ESDA as a Certified ESD Program Manager. He held positions as the ESD Program Manager for Western Digital Corporation and has been actively involved in the corporate ESD and contamination control programs at Seagate Technology and IBM Corporation. Carl has been a member of the ESD Association since 1995, actively participating as a board member, on many other major committees, and as a tutorial instructor. He currently is the ESD Association working group chairman of WG3 (Ionization) and WG28 (Electrostatic Attraction). He is co-author of "Contamination and ESD Control in High Technology Manufacturing", a book published by John Wiley & Sons.
Manufacturing Invited Talk: Air Ionization and it’s Use in Controlling Static Charge
EDA Interactive Workshop TBA
EDA Interactive Workshop TBA
Manufacturing Invited Talk - Healthcare TBA
Manufacturing Invited Talk - Healthcare TBA
EDA Invited Talk TBA
EDA Invited Talk TBA
Manufacturing Invited Talk - Electrostatic Discharge (ESD) Control in Healthcare
Thomas Ricciardelli
Tom Ricciardelli received a SB and SM in Chemical Engineering from MIT in 1985 and an MBA from the Sloan School of Management in 1991. In 1993, he founded SelecTech with the mission of creating valuable products from recycled materials. He has over 30 years of experience with developing unique polymer blends to meet demanding technical requirements and holds several patents for products and processes using recycled materials. He was the first to conceive of and develop an adhesive-free, interlocking static-control flooring system which paved the way for the StaticStop line of industry-leading ESD flooring products.
With this product, he was flung headlong into the ESD industry and joined the ESD Association in 2013 to become more involved in the industry and better understand the full needs of his customers. He is now the chair of WG 7 and WG29 and a member of WG19, WG28, WG4, and WG97. “While I have a strong engineering background with degrees in chemical engineering, my knowledge of electronics and ESD was certainly limited. Being involved in the ESD association, through the committees, the available training information, and generous support from other members, I’ve learned a vast amount about ESD and its control. I particularly enjoy networking with the other members, working with them on the committees, and having a little fun during the free time.”
Manufacturing Invited Talk - Electrostatic Discharge (ESD) Control in Healthcare
Afternoon Networking Break
Afternoon Networking Break
First Time Attendee and Emerging Professionals Reception
First Time Attendee and Emerging Professionals Reception
1A.1 Accuracy Preserving Extensions to a PDK MOSFET Model for ESD Simulation
Yujie Zhou
Yujie Zhou received the B.S. degree in electrical engineering from University of Illinois Urbana-Champaign (UIUC), Urbana, IL,USA, in 2019. He is currently pursuing the Ph.D. degree in electrical engineering with UIUC. His research interests include ESD, device physics, compact modeling, and TCAD.
1A.1 Accuracy Preserving Extensions to a PDK MOSFET Model for ESD Simulation
M1.1 In-Situ ESD Current Sensing in a Pick and Place Machine
Ellen Jirutková
Ellen Jirutková joined the Analysis & Test group at Fraunhofer EMFT in 2018 and has been supporting the team in researching topics related to electrostatic discharges. She received her Bachelor (2018) and Master degree (2021) at the Technical University of Munich (TUM), Germany. Since then, she has been working as research associate at Fraunhofer EMFT, specializing on ESD test methods, ESD robustness and protection and simulations. In 2022, she started to work on her PhD with the focus on ESD risks in Multi-Chip Modules (MCM) and Systems in Package (SiP). Ellen is an active member of the ESD Association and joined the steering committee of the International ESD Workshop 2023 in Tutzing, Germany.
M1.1 In-Situ ESD Current Sensing in a Pick and Place Machine
1A.2 CDM ESD Risk Assessment for Ground-Crossing Circuit Through PERC P2P/CD Programming
Kuo-Hsuan Meng
Kuo-Hsuan Meng received his B.S. degree from the Department of Electronics Engineering, and M.S. degree from the Institute of Electronics, National Chiao Tung University, Hsinchu, Taiwan, in 2006 and 2007, respectively. He received his Ph.D. degree from the Department of Electrical and Computer Engineering, University of Illinois Urbana-Champaign, in 2015. He worked at Freescale / NXP Semiconductors, Austin, TX, from 2015 to 2021. He joined Silicon Laboratories, Austin, TX, since 2021. His research interests include ESD protection network design, I/O library architecture, and CAD/EDA for SoC integration and ESD/latch-up design verification.
1A.2 CDM ESD Risk Assessment for Ground-Crossing Circuit Through PERC P2P/CD Programming
M1.2 Qualification Challenges of Conductive and Dissipative Plastics
Toni Viheriäkoski
Toni Viheriäkoski established electrostatics laboratory services for Nokia in 2001. He received iNARTE ESD engineer certification in 2004. Since 2008, he has been working on electrostatic and ESD risk analysis in healthcare, medical, electronics, automotive and process industries at Cascade Metrology Oy. Toni has written more than 30 publications. He has been the chair of the Finnish STAHA Association since 2006 and the chair of the Finnish Standardization Committee SK101 since 2016. He received specialist qualification in business management in 2018 and 1906 award of IEC in 2019. He is a member of several IEC and ESDA working groups.
M1.2 Qualification Challenges of Conductive and Dissipative Plastics
Author's Corner for 1A.1 and 1A.2
Kuo-Hsuan Meng
Kuo-Hsuan Meng received his B.S. degree from the Department of Electronics Engineering, and M.S. degree from the Institute of Electronics, National Chiao Tung University, Hsinchu, Taiwan, in 2006 and 2007, respectively. He received his Ph.D. degree from the Department of Electrical and Computer Engineering, University of Illinois Urbana-Champaign, in 2015. He worked at Freescale / NXP Semiconductors, Austin, TX, from 2015 to 2021. He joined Silicon Laboratories, Austin, TX, since 2021. His research interests include ESD protection network design, I/O library architecture, and CAD/EDA for SoC integration and ESD/latch-up design verification.
Yujie Zhou
Yujie Zhou received the B.S. degree in electrical engineering from University of Illinois Urbana-Champaign (UIUC), Urbana, IL,USA, in 2019. He is currently pursuing the Ph.D. degree in electrical engineering with UIUC. His research interests include ESD, device physics, compact modeling, and TCAD.
Author's Corner for 1A.1 and 1A.2
Authors Corner for M1.1 and M1.2
Ellen Jirutková
Ellen Jirutková joined the Analysis & Test group at Fraunhofer EMFT in 2018 and has been supporting the team in researching topics related to electrostatic discharges. She received her Bachelor (2018) and Master degree (2021) at the Technical University of Munich (TUM), Germany. Since then, she has been working as research associate at Fraunhofer EMFT, specializing on ESD test methods, ESD robustness and protection and simulations. In 2022, she started to work on her PhD with the focus on ESD risks in Multi-Chip Modules (MCM) and Systems in Package (SiP). Ellen is an active member of the ESD Association and joined the steering committee of the International ESD Workshop 2023 in Tutzing, Germany.
Toni Viheriäkoski
Toni Viheriäkoski established electrostatics laboratory services for Nokia in 2001. He received iNARTE ESD engineer certification in 2004. Since 2008, he has been working on electrostatic and ESD risk analysis in healthcare, medical, electronics, automotive and process industries at Cascade Metrology Oy. Toni has written more than 30 publications. He has been the chair of the Finnish STAHA Association since 2006 and the chair of the Finnish Standardization Committee SK101 since 2016. He received specialist qualification in business management in 2018 and 1906 award of IEC in 2019. He is a member of several IEC and ESDA working groups.
Authors Corner for M1.1 and M1.2
Manufacturing Hands-On Intro Presentation - Ionization
Carl Newberg
Carl Newberg is the manager of the Applications Engineering Team at Simco-Ion Technology, an ITW Company. Simco-Ion develops ionization solutions for high-technology semiconductor, electronics, and life science manufacturing. He has a B.S. degree in Metallurgical Engineering, an M.S. Degree in Materials Science, and a professional engineer’s license (Met. Eng.). He was among the first to test and receive certification from the ESDA as a Certified ESD Program Manager. He held positions as the ESD Program Manager for Western Digital Corporation and has been actively involved in the corporate ESD and contamination control programs at Seagate Technology and IBM Corporation. Carl has been a member of the ESD Association since 1995, actively participating as a board member, on many other major committees, and as a tutorial instructor. He currently is the ESD Association working group chairman of WG3 (Ionization) and WG28 (Electrostatic Attraction). He is co-author of "Contamination and ESD Control in High Technology Manufacturing", a book published by John Wiley & Sons.
Manufacturing Hands-On Intro Presentation - Ionization
1A.3 A Physics-Based Model for ESD Protection Devices with Open Base BJT Configuration
Seyed Mostafa Mousavi
Seyed Mostafa Mousavi (Senior Member, IEEE) received the B.Sc. degree from the Iran University of Sci. and Tech., Tehran, Iran, in 2007, and the M.Sc. and Ph.D. degrees from the K.N. Toosi University of Tech., Tehran, Iran, in 2010 and 2016, respectively, all in electrical engineering. In 2022, he joined Graz University of Technology, Graz, Austria before moving to the EMC Lab, Missouri University S&T, Rolla, MO, USA, where he is currently a Postdoctoral Fellow, specializing in EMC, ESD, and signal integrity.
1A.3 A Physics-Based Model for ESD Protection Devices with Open Base BJT Configuration
Manufacturing Hands-On Session - Ionization
Carl Newberg
Carl Newberg is the manager of the Applications Engineering Team at Simco-Ion Technology, an ITW Company. Simco-Ion develops ionization solutions for high-technology semiconductor, electronics, and life science manufacturing. He has a B.S. degree in Metallurgical Engineering, an M.S. Degree in Materials Science, and a professional engineer’s license (Met. Eng.). He was among the first to test and receive certification from the ESDA as a Certified ESD Program Manager. He held positions as the ESD Program Manager for Western Digital Corporation and has been actively involved in the corporate ESD and contamination control programs at Seagate Technology and IBM Corporation. Carl has been a member of the ESD Association since 1995, actively participating as a board member, on many other major committees, and as a tutorial instructor. He currently is the ESD Association working group chairman of WG3 (Ionization) and WG28 (Electrostatic Attraction). He is co-author of "Contamination and ESD Control in High Technology Manufacturing", a book published by John Wiley & Sons.
Manufacturing Hands-On Session - Ionization
1A.4 Substrate NPN Extraction from Capacitance Field Solver
Chuan Xu
Dr. Chuan Xu received the B.S. and the M.S. from Peking University. He received the Ph.D. from University of California at Santa Barbara in 2012. During his Ph.D. program, he interned with IBM T. J. Watson Research Center and Mentor Graphics Corporation. In 2012, he joined the Device Modeling Team of Legacy Maxim Integrated (acquired by Analog Devices since 2021). His current research interests include modeling of active devices, parasitic devices, interconnects and packages in VLSI circuits. He has authored or co-authored over 40 journal and conference papers.
1A.4 Substrate NPN Extraction from Capacitance Field Solver
Professional and Technical Women's Reception
Professional and Technical Women's Reception
1A.5 An Efficient and Cost-effective Method to Detect and Analyze ESD CDM Risks in Designs
Subhadeep Ghosh
Subhadeep Ghosh received his Bachelor's Degree in Electronics from Jadavpur University, Kolkata, India, and Masters Degree in Electronics from Indian Institute of Technology, Kharagpur, India. He joined Texas Instruments in Bangalore, India in 2005 and has since worked on Reliability EDA development for EMIR analysis, Transistor reliability and ESD. Currently he leads the EDA Development for Reliability, ESD and IR-drop analyses for all TI internal process nodes. He is a Member, Group Technical Staff (MGTS). His areas of expertise are design reliability, ESD EDA, digital design IR-drop, with methods enabling reliability as a specification through the design flow.
1A.5 An Efficient and Cost-effective Method to Detect and Analyze ESD CDM Risks in Designs
Authors Corner for 1A.3, 1A.4, and 1A.5
Subhadeep Ghosh
Subhadeep Ghosh received his Bachelor's Degree in Electronics from Jadavpur University, Kolkata, India, and Masters Degree in Electronics from Indian Institute of Technology, Kharagpur, India. He joined Texas Instruments in Bangalore, India in 2005 and has since worked on Reliability EDA development for EMIR analysis, Transistor reliability and ESD. Currently he leads the EDA Development for Reliability, ESD and IR-drop analyses for all TI internal process nodes. He is a Member, Group Technical Staff (MGTS). His areas of expertise are design reliability, ESD EDA, digital design IR-drop, with methods enabling reliability as a specification through the design flow.
Seyed Mostafa Mousavi
Seyed Mostafa Mousavi (Senior Member, IEEE) received the B.Sc. degree from the Iran University of Sci. and Tech., Tehran, Iran, in 2007, and the M.Sc. and Ph.D. degrees from the K.N. Toosi University of Tech., Tehran, Iran, in 2010 and 2016, respectively, all in electrical engineering. In 2022, he joined Graz University of Technology, Graz, Austria before moving to the EMC Lab, Missouri University S&T, Rolla, MO, USA, where he is currently a Postdoctoral Fellow, specializing in EMC, ESD, and signal integrity.
Chuan Xu
Dr. Chuan Xu received the B.S. and the M.S. from Peking University. He received the Ph.D. from University of California at Santa Barbara in 2012. During his Ph.D. program, he interned with IBM T. J. Watson Research Center and Mentor Graphics Corporation. In 2012, he joined the Device Modeling Team of Legacy Maxim Integrated (acquired by Analog Devices since 2021). His current research interests include modeling of active devices, parasitic devices, interconnects and packages in VLSI circuits. He has authored or co-authored over 40 journal and conference papers.
Authors Corner for 1A.3, 1A.4, and 1A.5
Welcome Reception and Exhibits Open
Welcome Reception and Exhibits Open
Tuesday, September 17
Registration Open
Registration Open
Morning Welcome
Morning Welcome
KEYNOTE: Charting the Connected Future
Daniel Cooley
Daniel Cooley serves as Chief Technology Officer and Senior Vice President, Technology and Product Development, where he is responsible for the company’s overall research and development strategy and execution. Cooley is a respected IoT industry veteran and has been instrumental in building the unmatched breadth and depth of the company’s wireless connectivity portfolio. Previously, Daniel served as Senior Vice President and Chief Strategy Officer, where he led Silicon Labs’ overall strategy, corporate development, M&A, emerging markets, and security. Prior to that, Daniel led Silicon Labs’ IoT business as Senior Vice President and General Manager. Since 2005, Cooley has served in a variety of engineering and business leadership positions at Silicon Labs in the US, Asia and Europe. He has an M.S. in Electrical Engineering from Stanford University and a B.S. in Electrical Engineering from The University of Texas at Austin and holds five patents in radio and low-power technology. Daniel currently serves on the board of directors for the Cockrell School of Engineering Advisory Board and the Austin Symphony Orchestra.
KEYNOTE: Charting the Connected Future
Exhibits Open - Coffee Available
Exhibits Open - Coffee Available
Activities in the Exhibit Hall - Guided Introduction Tour(s) to Meet the Exhibitors
Activities in the Exhibit Hall - Guided Introduction Tour(s) to Meet the Exhibitors
Networking Coffee Break in the exhibit hall
Networking Coffee Break in the exhibit hall
2A.1 ESD Behavior of RF Switches and Importance of System Efficient ESD Design (EMC+SIPI Exchange Paper)
Seyed Mostafa Mousavi
Seyed Mostafa Mousavi (Senior Member, IEEE) received the B.Sc. degree from the Iran University of Sci. and Tech., Tehran, Iran, in 2007, and the M.Sc. and Ph.D. degrees from the K.N. Toosi University of Tech., Tehran, Iran, in 2010 and 2016, respectively, all in electrical engineering. In 2022, he joined Graz University of Technology, Graz, Austria before moving to the EMC Lab, Missouri University S&T, Rolla, MO, USA, where he is currently a Postdoctoral Fellow, specializing in EMC, ESD, and signal integrity.
2A.1 ESD Behavior of RF Switches and Importance of System Efficient ESD Design (EMC+SIPI Exchange Paper)
Manufacturing Hands-On Intro Presentation - Personnel Grounding
Manufacturing Hands-On Intro Presentation - Personnel Grounding
2A.2 On-Chip ESD Protection for Multi-Gbps Automotive Serial IO in a 16-nm FinFET Process
Shudong Huang
2A.2 On-Chip ESD Protection for Multi-Gbps Automotive Serial IO in a 16-nm FinFET Process
Manufacturing Hands-on Session - Personnel Grounding
Manufacturing Hands-on Session - Personnel Grounding
2A.3 Influence of TVS Properties and Printed Circuit Board Design on System Level ESD Robustness for USB-C High-Speed Data Lines
Steffen Holland
Steffen Holland received his diploma and PhD in Physics from the University of Hamburg in 2004. He joined Philips Semiconductors/NXP/Nexperia in the process development group for discrete bipolar devices in Hamburg, Germany in 2005. The main focus of his work quickly became TCAD process and device simulations for discrete ESD protection devices. He works now on discrete ESD protection devices. His current interests are system level ESD simulations. He currently serves in the Board of Directors at the ESD Association and is chair of the ESDA working group 26.
2A.3 Influence of TVS Properties and Printed Circuit Board Design on System Level ESD Robustness for USB-C High-Speed Data Lines
Authors Corner for 2A.1, 2A.2, and 2A.3
Steffen Holland
Steffen Holland received his diploma and PhD in Physics from the University of Hamburg in 2004. He joined Philips Semiconductors/NXP/Nexperia in the process development group for discrete bipolar devices in Hamburg, Germany in 2005. The main focus of his work quickly became TCAD process and device simulations for discrete ESD protection devices. He works now on discrete ESD protection devices. His current interests are system level ESD simulations. He currently serves in the Board of Directors at the ESD Association and is chair of the ESDA working group 26.
Shudong Huang
Seyed Mostafa Mousavi
Seyed Mostafa Mousavi (Senior Member, IEEE) received the B.Sc. degree from the Iran University of Sci. and Tech., Tehran, Iran, in 2007, and the M.Sc. and Ph.D. degrees from the K.N. Toosi University of Tech., Tehran, Iran, in 2010 and 2016, respectively, all in electrical engineering. In 2022, he joined Graz University of Technology, Graz, Austria before moving to the EMC Lab, Missouri University S&T, Rolla, MO, USA, where he is currently a Postdoctoral Fellow, specializing in EMC, ESD, and signal integrity.
Authors Corner for 2A.1, 2A.2, and 2A.3
Activities in the Exhibit Hall - 20-minute In-Booth Demonstrations (parallel sessions)
Activities in the Exhibit Hall - 20-minute In-Booth Demonstrations (parallel sessions)
EMC Invited Talk: TBA
EMC Invited Talk: TBA
Manufacturing Invited Talk - Overview of all ESDA Control Standards
Wolfgang Stadler
Wolfgang Stadler received his diploma degree in physics in 1991 and in 1995 the PhD degree from the Physics Department of the Technical University Munich. 1995 he joined the semiconductor division of Siemens, which became Infineon Technologies in 1999. His focus was on development of ESD-protection concepts in CMOS technologies and on innovative ESD topics. In this role he was coordinator of several European and German ESD funding projects. Since 2003 he was also responsible for the measurement characterization of I/O cells and PHYs. 2011 he joined Intel Mobile Communications which is now Intel Germany Services GmbH. Within the Corporate Quality Network, he is currently responsible for the ESD Control Program of Intel and for ESD risk assessment. Furthermore, he supports ESD/latch-up testing and qualification of products. Wolfgang holds several patents in ESD-related topics. He is author or co-author of more than 120 technical papers and has co-authored a book on ESD simulation. He received several Best Paper Awards and gives regularly courses on ESD device testing, ESD qualification, and ESD control measures (for example, TR53 ESD Technician Certification). He is an active member of the EOS/ESD Association working groups related to device and system testing, ESD control, and ESD process assessment. He is also a member of STDCOM and TAS of the EOS/ESD Association. Currently he is the committee chair of the EOS/ESD Association Working Group 5.4 “Transient Latch-up” (since 2011) and the Working Group 12 “Seating”; since 2013 he has been co-chairing the ESDA Working Group 17 “Process Assessment”. Wolfgang has been elected to serve on the Board of Directors of the EOS/ESD Association for 2014–2019; 2015–2022 he was Education Business Unit Manager of the ESDA. Since 2015 he is acting as the president of the German ESD FORUM e.V. In 2019, he received the Outstanding Contribution Award of the EOS/ESD Association.
Manufacturing Invited Talk - Overview of all ESDA Control Standards
Light Networking Lunch in the exhibit hall
Light Networking Lunch in the exhibit hall
Workshop TBA
Workshop TBA
Workshop TBA
Workshop TBA
Afternoon Networking Break in the Exhibit Hall
Afternoon Networking Break in the Exhibit Hall
Photonics Invited Talk: TBA
Photonics Invited Talk: TBA
2B.1 Consideration of Waveform Analysis and Test Method for Charged Board Event (RCJ Exchange Paper)
Masanori Sawada
Masanori Sawada was born in Wakayama, Japan, 1973. He received his M.S. from Wakayama University in March 1998. He joined Hanwa Electronic Ind. in April 1998. Currently, he is the president of HANWA ELECTRONIC IND.
2B.1 Consideration of Waveform Analysis and Test Method for Charged Board Event (RCJ Exchange Paper)
Manufacturing Showcase Demonstrations - Seating, Bags, Process Assessment
Manufacturing Showcase Demonstrations - Seating, Bags, Process Assessment
2B.2 Proposing a Strategy to Prevent Module-level Charged Device Model Failures in Dual In-line Memory Modules
Youngbong Han
Youngbong Han received his B.S. degree in 2015 and his M.S. and Ph.D degrees in 2020 from the College of Information and Communication Engineering, Sungkyunkwan University, Suwon, South Korea. Since 2020, he has been working on quality assurance tasks related to Electromagnetic Compatibility, Electrostatic Discharge, and Signal Integrity at Samsung Electronics' Device Solutions Quality Synergy P/J.
2B.2 Proposing a Strategy to Prevent Module-level Charged Device Model Failures in Dual In-line Memory Modules
Standards Corner: Learn more about EOS/ESD Association, Inc. Standards
Standards Corner: Learn more about EOS/ESD Association, Inc. Standards
Authors Corner for 2B.1 and 2B.2
Youngbong Han
Youngbong Han received his B.S. degree in 2015 and his M.S. and Ph.D degrees in 2020 from the College of Information and Communication Engineering, Sungkyunkwan University, Suwon, South Korea. Since 2020, he has been working on quality assurance tasks related to Electromagnetic Compatibility, Electrostatic Discharge, and Signal Integrity at Samsung Electronics' Device Solutions Quality Synergy P/J.
Masanori Sawada
Masanori Sawada was born in Wakayama, Japan, 1973. He received his M.S. from Wakayama University in March 1998. He joined Hanwa Electronic Ind. in April 1998. Currently, he is the president of HANWA ELECTRONIC IND.
Authors Corner for 2B.1 and 2B.2
3A.1 ESD Robustness of Germanium Photodetectors in Advanced Silicon Photonics Technology
Shih-Hung Chen
Shih-Hung Chen has been with imec since 2010, and as ESD team lead and principal member of technical staff (PMTS) since 2019. He authored or co-authored more than 100 conference and journal publications. His current research interests include ESD protections in advanced sub-5nm technology nodes, in 3D/2.5D IC applications, and in Design Technology Co-Optimization (DTCO), System Technology Co-Optimization (STCO) with the integrations of III-V compounds.
3A.1 ESD Robustness of Germanium Photodetectors in Advanced Silicon Photonics Technology
2B.3 Intrinsic Inductance and Time-Dependent Resistance of the FI-CDM Spark
Timothy J. Maloney
Timothy J. Maloney graduated in physics and EE from MIT (SB 1971) and Cornell (MS 1973, PhD 1976). Following postdoctoral work at Cornell and semiconductor research at Varian Associates, Palo Alto, CA, he joined Intel Corp., Santa Clara, CA, in 1984, and has been concerned with IC ESD protection and testing, signal integrity, system ESD, and other topics. Dr. Maloney became a Senior Principal Engineer at Intel and retired in 2016. He has 40 patents, is co-author of a book, "Basic ESD and I/O Design" (Wiley, 1998), and is a Fellow of the IEEE. He has many publications at the EOS/ESD Symposium, IRPS, and other IEEE-connected entities.
2B.3 Intrinsic Inductance and Time-Dependent Resistance of the FI-CDM Spark
Manufacturing Showcase Demonstrations - Seating, Bags, Process Assessment
Manufacturing Showcase Demonstrations - Seating, Bags, Process Assessment
3A.2 ESD-EOS-OVP Protection Network for Battery Pins
Vladislav Vashchenko
Dr. Vladislav Vashchenko is currently Sr. Director Power ESD Group at Analog Devices Corp since 2011. He is responsible for aspects of power analog ESD/Latchup IC co-design business process and technology development. Previously he managed ESD technology development at National Semiconductor (2000-2011). He received MS Engineer-Physicist (1987), Ph.D. in Physics of Semiconductors from MIPT (1990), "Doctor of Science in Microelectronics" habilitation degree (1997). He is author of 150 U.S. patents, over 120 papers, co-author of the three books in ESD field.
3A.2 ESD-EOS-OVP Protection Network for Battery Pins
2B.4 The Demand for a CDM Bare Die Testing Method
Lena Zeitlhoefler
Lena Zeitlhöfler received her Master's degree in Electrical Engineering in 2017 from the Technical University of Munich (TUM). During her time as a Ph.D. student at the TUM, she worked in cooperation with Infineon Technologies AG in the fields of ESD and, particularly, on the physics of CDM and CDM simulation. She joined the ESD Team of Infineon in Munich, Germany, full-time in September 2021.
2B.4 The Demand for a CDM Bare Die Testing Method
3A.3 Bidirectional DIAC Devices with Two-Stage Triggering
Michael Amato
Michael Amato graduated from Rensselaer Polytechnic Institute with a BSEE in ‘82 and MSEE in '84, with emphasis in semiconductor device and IC technology. At Philips Research he led teams developing new monolithic Power IC technologies and TFT arrays for LCD HDTV. Working at Allegro Microsystems & CPClare (IXYS), he also directed CAD/PDK development and device modeling. In 2004 he joined Linear Technology Corp (now Analog Devices Inc) directing all ESD Co-design and new ESD device development for in-house and foundry processes, developing unique ESD solutions for High Voltage, Power, Analog, Digital, and Mixed Signal ICs.
3A.3 Bidirectional DIAC Devices with Two-Stage Triggering
2B.5 FI-CDM and LICCDM Testing on Wafer, Single Die, and Package Levels
Marko Simicic
Marko Simicic received the M.Sc. degree in electrical engineering and information technology from the University of Zagreb, Croatia, in 2012. He obtained a PhD degree from the department of electrical engineering ESAT, KU Leuven, Belgium in 2018. Since 2017 he is an ESD researcher in imec, Belgium. He is a certified ESD control program manager since 2022. He has authored or co-authored more than 40 papers in international journals and conference proceedings. His current research area is rather wide and includes ESD device and circuit design in advanced semiconductor and 3D/2.5D stacking technologies, novel ESD testing and ESD control process assessment.
2B.5 FI-CDM and LICCDM Testing on Wafer, Single Die, and Package Levels
Authors Corner for 3A.1, 3A.2, and 3A.3
Michael Amato
Michael Amato graduated from Rensselaer Polytechnic Institute with a BSEE in ‘82 and MSEE in '84, with emphasis in semiconductor device and IC technology. At Philips Research he led teams developing new monolithic Power IC technologies and TFT arrays for LCD HDTV. Working at Allegro Microsystems & CPClare (IXYS), he also directed CAD/PDK development and device modeling. In 2004 he joined Linear Technology Corp (now Analog Devices Inc) directing all ESD Co-design and new ESD device development for in-house and foundry processes, developing unique ESD solutions for High Voltage, Power, Analog, Digital, and Mixed Signal ICs.
Shih-Hung Chen
Shih-Hung Chen has been with imec since 2010, and as ESD team lead and principal member of technical staff (PMTS) since 2019. He authored or co-authored more than 100 conference and journal publications. His current research interests include ESD protections in advanced sub-5nm technology nodes, in 3D/2.5D IC applications, and in Design Technology Co-Optimization (DTCO), System Technology Co-Optimization (STCO) with the integrations of III-V compounds.
Vladislav Vashchenko
Dr. Vladislav Vashchenko is currently Sr. Director Power ESD Group at Analog Devices Corp since 2011. He is responsible for aspects of power analog ESD/Latchup IC co-design business process and technology development. Previously he managed ESD technology development at National Semiconductor (2000-2011). He received MS Engineer-Physicist (1987), Ph.D. in Physics of Semiconductors from MIPT (1990), "Doctor of Science in Microelectronics" habilitation degree (1997). He is author of 150 U.S. patents, over 120 papers, co-author of the three books in ESD field.
Authors Corner for 3A.1, 3A.2, and 3A.3
Authors Corner for 2B.3, 2B.4, and 2B.5
Authors Corner for 2B.3, 2B.4, and 2B.5
Semiconductor Fab ESD/Electrostatic Attraction (ESA) Controls Discussion Group
Larry Levit
Dr. Larry Levit provides a variety of ESD consulting services as LBL Scientific. He was Global ESD program Manager for Finisar Corporation and Chief Scientist for MKS, Ion Systems, He has over 20 years of experience in the field of ESD control. He is a NARTE Certified ESD Engineer. Levit has audited cleanrooms on three continents and is recognized as a problem solver. He has successfully devised solutions to manufacturing problems to reduce ESD yield loss, contamination issues and reticle damage. Before joining MKS, Ion Systems, Levit held technical rolls at LeCroy Corporation and Jandel Scientific Software. At LeCroy, he contributed to the instrumentation designs for 6 experiments which produced Nobel prizes in physics. Levit taught physics at CWRU, LSU, and at Napa Valley Community College. He is a senior member of the ESD Association, a senior member of the IEST and chairs the WG CC022 Working Group for IEST. Levit graduated from Case Institute of Technology, Cleveland, Ohio with a BS degree in physics with honors. He then went on to earn a Ph.D. in Experimental High Energy Physics from Case Western Reserve University.
Andrew Nold
Andy Nold is a Quality Engineer and Commodity Engineer at Teradyne near Chicago, IL. He is the Factory ESD subject matter expert and performs the company’s internal ESD audits. He has worked for Teradyne since 2011.
Prior to Teradyne, Andy worked for the FAA, a small aerospace company, and the US Navy. Andy graduated from the University of Wisconsin with a bachelor’s degree in Applied Math, Engineering, and Physics and a master’s degree in Engineering Mechanics.
Outside of work, Andy likes to spend time with his wife and kids.
Semiconductor Fab ESD/Electrostatic Attraction (ESA) Controls Discussion Group
Volunteer Showcase Reception - Open to All Attendees
Volunteer Showcase Reception - Open to All Attendees
Wednesday, September 18
Registration Open
Registration Open
Morning Welcome
Morning Welcome
KEYNOTE: Advanced Failure Analysis Techniques and Workflows for 3D Packaged Devices
Frank Altman
Frank Altmann received his Diploma in Physics from the Technical University, Dresden. He joined the Fraunhofer IWM (now IMWS) in 1997 and has since been concerned with material diagnostics and failure analysis of semiconductor components. Since 2006, he has been head of the research group Diagnostics of Semiconductor Technologies, with responsibility for national and international research projects with industry and public organizations focusing on 3D packaging and Si and GaN chip technologies. Since 2019, he has been acting head of the department of Electronic Materials and Components. Frank Altmann has authored and co-authored more than 130 publications, is active within several national and international failure analysis conferences and education committees, and was the general chair of ISTFA 2023.
KEYNOTE: Advanced Failure Analysis Techniques and Workflows for 3D Packaged Devices
Exhibits Open - Coffee Available
Exhibits Open - Coffee Available
Activities in the Exhibit Hall - 20-minute In-Booth Demonstrations (parallel sessions)
Activities in the Exhibit Hall - 20-minute In-Booth Demonstrations (parallel sessions)
Networking Coffee Break in the exhibit hall
Networking Coffee Break in the exhibit hall
4A.1 Transistor Layout and Technology Impacts on ESD HBM Performance of GaN-on-SiC RF HEMTs
Wei-Min Wu
Wei-Min Wu received the dual-Ph.D. degrees in electrical engineering from the KU Leuven, Belgium, and in electronic engineering from National Yang Ming Chiao Tung University (NYCU), Taiwan in 2022. He is now with IMEC, Leuven, Belgium as an RF ESD researcher. His current research interests include ESD protections in Design Technology Co-Optimization (DTCO) with the Si/III-V RF devices and circuits and in high-speed I/O technology.
4A.1 Transistor Layout and Technology Impacts on ESD HBM Performance of GaN-on-SiC RF HEMTs
3B.1 A Statistical Explanation of CDM Qualification Variability
Theo Smedes
After receiving his Ph.D. from the Eindhoven University of Technology with a thesis on compact device modelling, Theo Smedes worked at the Delft University of Technology on layout-to-circuit extraction. In 1995 he joined NXP Semiconductors (Philips Semiconductors at that time), working on tools for statistical design. Currently, he is NXP Fellow for ESD and Latch-up. Theo is member of all ESDA device testing working groups and chairs the TLP working group. He published several papers on ESD and received the 2007 Best Paper Award and the 2009, 2018 and 2022 Outstanding Paper Award of the EOS/ESD Symposium. Theo was general chair of the EOS/ESD Symposium in 2013. He has been recognized with ESDA's David F. Barber Sr. Memorial Award (2017) and Outstanding Contribution Award (2022).
3B.1 A Statistical Explanation of CDM Qualification Variability
Manufacturing Showcase Demonstrations - Seating, Bags, Process Assessment
Manufacturing Showcase Demonstrations - Seating, Bags, Process Assessment
4A.2 ESD Protection Analysis for 3D NAND Internal Source Plate Discharge Circuit
James Davis
James Davis received a B.S. degree in electrical engineering from Brigham Young University (Provo, Utah USA) in 2002. He has been involved with on-chip ESD protection at Micron Technology, Inc. (Boise, Idaho USA) for the past twenty years. He is currently part of the R&D group focusing on on-chip ESD protection and design for NAND flash products. Mr. Davis is currently a Senior Member Technical Staff ESD/Latchup engineer.
4A.2 ESD Protection Analysis for 3D NAND Internal Source Plate Discharge Circuit
3B.2 Secondary Discharges during FICDM stress - Source and Solution
Sheela Verwoerd
Sheela Verwoerd received her M.Sc in Applied Physics in 2000 at the Indian Institute of Technology, Madras, India. She then moved to the Netherlands, where she did her PhD on "Full Chip Modelling of ICs under CDM stress" in the University of Twente in Enschede. She worked as ESD Assurance Engineer at Philips Semiconductors for a couple of years. After a brief gap of 10 years, she joined NXP Semiconductors as Principal ESD/LU test Engineer. She had been focused on ESD/LU qualification of ICs since then.
3B.2 Secondary Discharges during FICDM stress - Source and Solution
4A.3 Efficient Pre-Silicon ESD Verification for Enabling High Performance IO Design
Priya Walimbe
Priya Walimbe has a master's degree in EE wand 25 years of experience in High Speed IO and Analog design. Currently, she is a Principal Engineer at Intel, providing technical leadership for innovations in state-of-the-art IO design and methodologies. She one of the leaders in architecture and design of several generations of DDR/LPDDR PHYs. She has heavily contributed to design technology co-optimization on Intel internal and external foundry. Priya has been an active member of ESD community at Intel, leading ESD design and verification improvements and innovations. She holds 6 patents, authored/co-authored many publications. She's art loving and enjoys classical music.
4A.3 Efficient Pre-Silicon ESD Verification for Enabling High Performance IO Design
3B.3 System CDM Modeling for High-Speed Interface Devices
Emanuele Groppo
Emanuele Groppo received his B.Sc. (2020) and M.Sc. (2022) in Electronic Engineering from Politecnico di Torino, Italy. He is currently pursuing a Ph.D. at the Technical University of Munich (TUM), Chair of Circuit Design. In 2023, he joined the ESD team at Intel in Munich, Germany. The focus of his research is on novel ESD devices and solutions for advanced semiconductor technologies.
3B.3 System CDM Modeling for High-Speed Interface Devices
Authors Corner for 4A.1, 4A.2, and 4A.3
James Davis
James Davis received a B.S. degree in electrical engineering from Brigham Young University (Provo, Utah USA) in 2002. He has been involved with on-chip ESD protection at Micron Technology, Inc. (Boise, Idaho USA) for the past twenty years. He is currently part of the R&D group focusing on on-chip ESD protection and design for NAND flash products. Mr. Davis is currently a Senior Member Technical Staff ESD/Latchup engineer.
Priya Walimbe
Priya Walimbe has a master's degree in EE wand 25 years of experience in High Speed IO and Analog design. Currently, she is a Principal Engineer at Intel, providing technical leadership for innovations in state-of-the-art IO design and methodologies. She one of the leaders in architecture and design of several generations of DDR/LPDDR PHYs. She has heavily contributed to design technology co-optimization on Intel internal and external foundry. Priya has been an active member of ESD community at Intel, leading ESD design and verification improvements and innovations. She holds 6 patents, authored/co-authored many publications. She's art loving and enjoys classical music.
Wei-Min Wu
Wei-Min Wu received the dual-Ph.D. degrees in electrical engineering from the KU Leuven, Belgium, and in electronic engineering from National Yang Ming Chiao Tung University (NYCU), Taiwan in 2022. He is now with IMEC, Leuven, Belgium as an RF ESD researcher. His current research interests include ESD protections in Design Technology Co-Optimization (DTCO) with the Si/III-V RF devices and circuits and in high-speed I/O technology.
Authors Corner for 4A.1, 4A.2, and 4A.3
Authors Corner for 3B.1, 3B.2, and 3B.3
Emanuele Groppo
Emanuele Groppo received his B.Sc. (2020) and M.Sc. (2022) in Electronic Engineering from Politecnico di Torino, Italy. He is currently pursuing a Ph.D. at the Technical University of Munich (TUM), Chair of Circuit Design. In 2023, he joined the ESD team at Intel in Munich, Germany. The focus of his research is on novel ESD devices and solutions for advanced semiconductor technologies.
Theo Smedes
After receiving his Ph.D. from the Eindhoven University of Technology with a thesis on compact device modelling, Theo Smedes worked at the Delft University of Technology on layout-to-circuit extraction. In 1995 he joined NXP Semiconductors (Philips Semiconductors at that time), working on tools for statistical design. Currently, he is NXP Fellow for ESD and Latch-up. Theo is member of all ESDA device testing working groups and chairs the TLP working group. He published several papers on ESD and received the 2007 Best Paper Award and the 2009, 2018 and 2022 Outstanding Paper Award of the EOS/ESD Symposium. Theo was general chair of the EOS/ESD Symposium in 2013. He has been recognized with ESDA's David F. Barber Sr. Memorial Award (2017) and Outstanding Contribution Award (2022).
Sheela Verwoerd
Sheela Verwoerd received her M.Sc in Applied Physics in 2000 at the Indian Institute of Technology, Madras, India. She then moved to the Netherlands, where she did her PhD on "Full Chip Modelling of ICs under CDM stress" in the University of Twente in Enschede. She worked as ESD Assurance Engineer at Philips Semiconductors for a couple of years. After a brief gap of 10 years, she joined NXP Semiconductors as Principal ESD/LU test Engineer. She had been focused on ESD/LU qualification of ICs since then.
Authors Corner for 3B.1, 3B.2, and 3B.3
Emerging Technologies Invited Talk: Root Cause Categories for Electrical Over-Stress (EOS) and Electrically Induced Physical Damage (EIPD) on Customer Returns and Qualification Failures
Alfred J. Griffin, Jr.
Al Griffin joined Texas Instruments, Inc. in 1996, and was elected Senior Fellow in February 2020. He has over 30 years of experience in metallurgy, materials science, materials reliability and materials integration, particularly with respect to semiconductor and printed circuit board manufacturing. Al Griffin manages some of TI’s most critical customer return, excursion and qualification issues across all of TI’s technologies and factories and is a founding member of The Red Team, a problem-solving organization. He has worked with most of TI’s top engineers, designers and customers and has collaborated across TI to solve customers’ problems and a wide range of worldwide TI wafer fab and AT issues. Al received his B.S. in Metallurgical Engineering from the University of Texas at El Paso and his Ph.D. and M.S. in Materials Science from Rice University.
Emerging Technologies Invited Talk: Root Cause Categories for Electrical Over-Stress (EOS) and Electrically Induced Physical Damage (EIPD) on Customer Returns and Qualification Failures
Device Testing Invited Talk TBA
Device Testing Invited Talk TBA
Light Networking Lunch in the exhibit hall
Light Networking Lunch in the exhibit hall
Factory Controls Ionization Workshop
Factory Controls Ionization Workshop
Workshop TBA
Workshop TBA
Afternoon Networking Break
Afternoon Networking Break
Emerging Technologies Talk TBA
Emerging Technologies Talk TBA
Manufacturing Invited Paper - Static Control for Roll to Roll Manufacturing
Kelly Robinson
Kelly has over 35 years of industrial experience solving manufacturing problems and commercializing new products. Dr. Robinson holds the PhD in electrical engineering (Colorado State University), is a Professional Engineer (New York), and is a Patent Agent. Previously, he worked at the Eastman Kodak Company for 25 years developing and commercializing copier technologies, imaging products, and controlling static in roll-to-roll manufacturing of photographic papers and films where the light from static sparks caused customer observable product defects. In 2007, he founded Electrostatic Answers, an engineering consulting company dedicated to eliminating injury and waste from static electricity, which has served over 100 clients including many Fortune 500 companies. Kelly is an IEEE Fellow (2011) cited for contributions to the static performance of manufacturing operations, chairs the National Fire Protection Assoc. (NFPA) Static Electricity Committee (2018), is an associate editor of the Journal of Electrostatics (2015), a contributing editor on static control (2009) for Paper, Film & Foil Converter (PFFC), serves on the Technical Advisory Panel (2019) of the Association of International Metallizers, Coaters, and Laminators (AIMCAL), and is the inventor on 15 issued US patents. He has authored over 90 trade articles and peer reviewed publications on applied electrostatics.
Manufacturing Invited Paper - Static Control for Roll to Roll Manufacturing
Emerging Technologies Talk TBA
Emerging Technologies Talk TBA
M2.1 Static Cracking Due to Electro-Static Discharge During Glass Substrate Transferring System in Vacuum
DongSun Kim
DongSun Kim received a PhD in Materials Science from Korea University. His research interests are how to improve products yield include circuit design, process integration, and adoption of materials in contact with products based on dissipative polymers directed towards prevention ESD in display and semiconductor industry. He has worked in LG Semiconductor since 1992 and currently working as an engineering fellow in LG Display.
M2.1 Static Cracking Due to Electro-Static Discharge During Glass Substrate Transferring System in Vacuum
M2.2 Using Discharge Current Measurements in Risk Assessments
Istvan Kovalik
Istvan Kovalik began his work in the field of ESD control in 2003. He's been working as an ESD Coordinator at Harman for 9 years, and responsible for all aspects of ESD control in 3 facilities in his country. He performs some volunteer works for ESDA and received his ESD Program Manager Certification in 2023.
M2.2 Using Discharge Current Measurements in Risk Assessments
Networking Break
Networking Break
Authors Corner for M2.1 and M2.2
DongSun Kim
DongSun Kim received a PhD in Materials Science from Korea University. His research interests are how to improve products yield include circuit design, process integration, and adoption of materials in contact with products based on dissipative polymers directed towards prevention ESD in display and semiconductor industry. He has worked in LG Semiconductor since 1992 and currently working as an engineering fellow in LG Display.
Istvan Kovalik
Istvan Kovalik began his work in the field of ESD control in 2003. He's been working as an ESD Coordinator at Harman for 9 years, and responsible for all aspects of ESD control in 3 facilities in his country. He performs some volunteer works for ESDA and received his ESD Program Manager Certification in 2023.
Authors Corner for M2.1 and M2.2
5A.1 TDDB of Sensitive Gate Dielectrics – Revisited for CDM
Christian C. Russ
Dr. Christian Russ received his MS and PhD degrees in electrical engineering from the Technical University of Munich, Germany, in 1991 and 1999, respectively. He has spent more than 30 years in the field of ESD: from 1994 through 1998, he was with IMEC, Leuven, Belgium, and from 1998 through 2003 he worked for Sarnoff Corporation, Princeton, New Jersey, USA. In 2003, he joined Infineon Technologies, Munich, Germany. In 2011, he transferred to Intel Mobile Communications where he developed ESD concepts for planar and FinFET CMOS technologies. Since 2017, he has been at Infineon Technologies as lead principal engineer for ESD solutions in automotive sensor technologies (Smart Power, CMOS, BiCMOS). Christian was recipient of several Best Paper Awards at the EOS/ESD Symposia (1993, 1996, 1998, 2000, 2001, 2005, 2012 and 2021) and at the ESREF Conference (1993, 1995). He has published over 75 conference and journal publications and has been awarded over 80 patents in his field.
5A.1 TDDB of Sensitive Gate Dielectrics – Revisited for CDM
Manufacturing Hands-On Intro Presentation - Process Assessment
Manufacturing Hands-On Intro Presentation - Process Assessment
5A.2 Self-Sufficient ESD Solution for Fail-safe I/O Design in FinFET technology
Hsin-Yu Chen
Hsin-Yu Chen received the B.S. degree from the Department of Applied Physics, National University of Kaohsiung, Kaohsiung, Taiwan, in 2016, and the M.S. degree from the Institute of Electrophysics, National Chiao-Tung University, Hsinchu, Taiwan, in 2019. She joined Taiwan Semiconductor Manufacturing Company (TSMC) in 2019 and she is in ESD/EOS Technology Department.
5A.2 Self-Sufficient ESD Solution for Fail-safe I/O Design in FinFET technology
Manufacturing Hands-On Session - Process Assessment
Manufacturing Hands-On Session - Process Assessment
5A.3 Single Event Latch-up (SEL) Rate Prediction Methodology in Bulk FinFET Technology
Tzu-Hao Chiang
Tzu-Hao Chiang received the B.S. degree in electrical engineering and the M.S. degree in electronic engineering from National Taiwan University, Taipei, Taiwan, in 2020. He joined Taiwan Semiconductor Manufacturing Company (TSMC) in 2020, where he is currently a Senior Engineer in ESD/EOS Technology Department. His work is mainly on single event latchup (SEL) and ESD victim design solution development.
5A.3 Single Event Latch-up (SEL) Rate Prediction Methodology in Bulk FinFET Technology
Authors Corner for 5A.1, 5A.2, and 5A.3
Hsin-Yu Chen
Hsin-Yu Chen received the B.S. degree from the Department of Applied Physics, National University of Kaohsiung, Kaohsiung, Taiwan, in 2016, and the M.S. degree from the Institute of Electrophysics, National Chiao-Tung University, Hsinchu, Taiwan, in 2019. She joined Taiwan Semiconductor Manufacturing Company (TSMC) in 2019 and she is in ESD/EOS Technology Department.
Tzu-Hao Chiang
Tzu-Hao Chiang received the B.S. degree in electrical engineering and the M.S. degree in electronic engineering from National Taiwan University, Taipei, Taiwan, in 2020. He joined Taiwan Semiconductor Manufacturing Company (TSMC) in 2020, where he is currently a Senior Engineer in ESD/EOS Technology Department. His work is mainly on single event latchup (SEL) and ESD victim design solution development.
Christian C. Russ
Dr. Christian Russ received his MS and PhD degrees in electrical engineering from the Technical University of Munich, Germany, in 1991 and 1999, respectively. He has spent more than 30 years in the field of ESD: from 1994 through 1998, he was with IMEC, Leuven, Belgium, and from 1998 through 2003 he worked for Sarnoff Corporation, Princeton, New Jersey, USA. In 2003, he joined Infineon Technologies, Munich, Germany. In 2011, he transferred to Intel Mobile Communications where he developed ESD concepts for planar and FinFET CMOS technologies. Since 2017, he has been at Infineon Technologies as lead principal engineer for ESD solutions in automotive sensor technologies (Smart Power, CMOS, BiCMOS). Christian was recipient of several Best Paper Awards at the EOS/ESD Symposia (1993, 1996, 1998, 2000, 2001, 2005, 2012 and 2021) and at the ESREF Conference (1993, 1995). He has published over 75 conference and journal publications and has been awarded over 80 patents in his field.
Authors Corner for 5A.1, 5A.2, and 5A.3
General Chair's Reception and TEsD Talk "Shockingly Enlightening: A Jolting Recap of the 2024 EOS/ESD Symposium" (Open to All Attendees)
Brennan Pimpinella
Jay Skolnik
Jay Skolnik is a licensed professional electrical engineer and is the co-founder and lead engineer/consultant of Skolnik Technical Training in Albuquerque, NM. With over thirty years of experience in the electronics industry, Jay has developed a multitude of products utilized in different industries, including military, defense, avionics, aerospace, commercial, industrial, medical, automotive, and sports entertainment.
As an ESDA certified program manager, Jay teaches ESD mitigation and control for the electronics and energetics specialties. He performs ESD audits to ensure factories and laboratories are following safe ESD control guidelines and procedures. He is also certified by iNARTE and is a certified professional instructor of national instruments (NI). He received his electrical engineering degree from the University of Missouri-Rolla.