Monday, September 16
Opening Welcome
Opening Welcome
Keynote - Memory Technology Advancements Driving High Performance, Reliable Systems
![Chandra Mouli](/assets/Presenters/Chandra-Mouli__FillMaxWzYwMCw2MDBd.jpg)
Chandra Mouli
Chandra Mouli is with Micron Technology Inc., Boise, ID, USA. He is currently Vice President of Device Technology R&D with responsibilities in the areas of device characterization, reliability analysis, compact models, test structure design, process & device modeling for all technologies under development in R&D. He received his undergraduate degree in Physics and MSEE from the Indian Institute of Science (IISc), Bangalore, India and Ph.D. (EE) from the University of Texas at Austin in 1994. He has previously worked at Texas Instruments Inc. He was a visiting scholar (VSRP program) at the Tata Institute of Fundamental Research (TIFR) and has been an intern at the Defense Electronics Application Lab (DEAL) in Dehra Dun. His interests include semiconductor devices and process technology for advanced memory, optoelectronic devices, and exploratory research in the area of new materials and device structures. He has ~500 issued patents and several pending in various areas of semiconductor devices and processes – in advanced memory, novel exploratory devices, image sensors, high-speed interconnects, and related technologies. He has served on the technical committees for various conferences, including IEDM, IRPS, and SISPAD. He has also served on the review committees for NSF and SRC and as an editor for IEEE Electron Device Letters (EDL).
Keynote - Memory Technology Advancements Driving High Performance, Reliable Systems
Networking Break
Networking Break
EDA Invited Talk - Applications of Machine Learning to Microelectronics (and ESD) Design
![Elyse Rosenbaum](/assets/Presenters/Elyse-Rosenbaum__FillMaxWzYwMCw2MDBd.jpg)
Elyse Rosenbaum
Elyse Rosenbaum is the Melvin and Anne Louise Hassebrock Professor in Electrical and Computer Engineering at the University of Illinois Urbana-Champaign. She received a Ph.D. in electrical engineering from University of California, Berkeley. She is the director of the NSF-supported Center for Advanced Electronics through Machine Learning (CAEML), a joint project of the University of Illinois, North Carolina State University, and Penn State. Her current research interests include CDM-ESD reliability, ESD-robust high-speed I/O circuit design, compact modeling, optimization of heterogeneously integrated system-in-package, machine learning aided modeling of circuit lifetime distributions, and explainable models of analog circuits.
Dr. Rosenbaum has authored or co-authored over 200 technical papers; she has been an editor for IEEE Transactions on Device and Materials Reliability and IEEE Transactions on Electron Devices. She served as the General Chair of the 2018 International Reliability Physics Symposium. Dr. Rosenbaum was the recipient of a Best Student Paper Award from the IEDM, an Outstanding Paper Award and 2 Best Paper Awards from the EOS/ESD Symposium, a Technical Excellence Award from the SRC, an NSF CAREER award, an IBM Faculty Award, and the ESD Association’s Industry Pioneer Recognition Award. She is a Fellow of the IEEE.
EDA Invited Talk - Applications of Machine Learning to Microelectronics (and ESD) Design
EDA Invited Talk - ESD Reliability in Advanced Nodes
![Steven S. Poon](/assets/Presenters/bio2024__FillMaxWzYwMCw2MDBd.jpg)
Steven S. Poon
Steven S. Poon has dedicated his career to electrostatic discharge (ESD) and latch-up (LU) since late 1999. He received the B.Sc. and M.Eng. degrees in Electrical Engineering from Cornell University, Ithaca, NY. He joined Intel Corporation thereafter and was responsible for various ESD/LU-related functions at different parts of his career there, including protection structure development, process certification, design rules and guidelines, product co-design and sign-off, EDA tools, and system-level ESD design. His experience at Intel spanned all technologies nodes from 0.13um to 5nm, including the ESD/LU development work enabling the smooth transition to copper interconnect, high-k/metal gate, FinFET and 3DIC. While at Intel, he pioneered the use of ESD simulation techniques not just for IP co-design, but also chip-level sign-off. He has published various papers at IEEE-sponsored conferences and contributed to tutorials and industry technical reports. He later joined the Quality and Reliability organization of TSMC in 2021 and is responsible for ESD-related functions handled by the organization.
EDA Invited Talk - ESD Reliability in Advanced Nodes
Networking Break
Networking Break
EDA Interactive Presentation and Workshop - ESD Electronic Design Automation Challenges - New Revision of ESDA Technical Report ESD TR18.0-01
![Michael Khazhinsky](/assets/Presenters/Michael-Khazhinsky-v2__FillMaxWzYwMCw2MDBd.jpg)
Michael Khazhinsky
Michael G. Khazhinsky is currently a Principal ESD engineer/designer at Silicon Labs in Austin, Texas. Prior to joining Silicon Labs, he worked at Motorola and Freescale Semiconductors where he was in charge of the TCAD development and ESD/latch-up protection solutions for emerging process technologies, with a focus on ESD-EDA. Michael has M.S.E.E. and M.S. Physics from the Moscow State Institute of Electronic Engineering, and Ph.D. in Physics from Western Michigan University. Michael is the Chair of ESDA Working Group 18 on EDA. Michael has served as a member of the IRPS, IEW, ESREF, EMC and EOS/ESD Symposium Technical Program Committees, as well as a Workshop Chair, Technical Program Chair, Vice General Chair and General Chair of EOS/ESD Symposium. He currently serves on the Technical Program Committees of 2019 International Reliability Physics Symposium, 2019 EMC Symposium, 2019 ESREF and 2019 EOS/ESD Symposium. Michael co-authored over 30 papers and gave a number of invited talks on ESD, EDA, process/device TCAD, and photonic crystals. He was a co-recipient of seven EOS/ESD Symposium and SOI Symposium “Best Paper” and “Best Presentation” awards. Michael currently holds eighteen patents on ESD design, with additional patents pending. Michael is a Senior Member of IEEE and the Director of the ESD Association.
EDA Interactive Presentation and Workshop - ESD Electronic Design Automation Challenges - New Revision of ESDA Technical Report ESD TR18.0-01
1A.1 Accuracy Preserving Extensions to a PDK MOSFET Model for ESD Simulation
![Yujie Zhou](/assets/Presenters/Yujie-Zhou__FillMaxWzYwMCw2MDBd.jpg)
Yujie Zhou
Yujie Zhou received the B.S. degree in electrical engineering from University of Illinois Urbana-Champaign (UIUC), Urbana, IL,USA, in 2019. He is currently pursuing the Ph.D. degree in electrical engineering with UIUC. His research interests include ESD, device physics, compact modeling, and TCAD.
1A.1 Accuracy Preserving Extensions to a PDK MOSFET Model for ESD Simulation
1A.2 CDM ESD Risk Assessment for Ground-Crossing Circuit Through PERC P2P/CD Programming
![Kuo-Hsuan Meng](/assets/Presenters/Kuo-Hsuan-Meng-v2__FillMaxWzYwMCw2MDBd.png)
Kuo-Hsuan Meng
Kuo-Hsuan Meng received his B.S. degree from the Department of Electronics Engineering, and M.S. degree from the Institute of Electronics, National Chiao Tung University, Hsinchu, Taiwan, in 2006 and 2007, respectively. He received his Ph.D. degree from the Department of Electrical and Computer Engineering, University of Illinois Urbana-Champaign, in 2015. He worked at Freescale / NXP Semiconductors, Austin, TX, from 2015 to 2021. He joined Silicon Laboratories, Austin, TX, since 2021. His research interests include ESD protection network design, I/O library architecture, and CAD/EDA for SoC integration and ESD/latch-up design verification.
1A.2 CDM ESD Risk Assessment for Ground-Crossing Circuit Through PERC P2P/CD Programming
Author's Corner for 1A.1 and 1A.2
![Kuo-Hsuan Meng](/assets/Presenters/Kuo-Hsuan-Meng-v2__FillMaxWzYwMCw2MDBd.png)
Kuo-Hsuan Meng
Kuo-Hsuan Meng received his B.S. degree from the Department of Electronics Engineering, and M.S. degree from the Institute of Electronics, National Chiao Tung University, Hsinchu, Taiwan, in 2006 and 2007, respectively. He received his Ph.D. degree from the Department of Electrical and Computer Engineering, University of Illinois Urbana-Champaign, in 2015. He worked at Freescale / NXP Semiconductors, Austin, TX, from 2015 to 2021. He joined Silicon Laboratories, Austin, TX, since 2021. His research interests include ESD protection network design, I/O library architecture, and CAD/EDA for SoC integration and ESD/latch-up design verification.
![Yujie Zhou](/assets/Presenters/Yujie-Zhou__FillMaxWzYwMCw2MDBd.jpg)
Yujie Zhou
Yujie Zhou received the B.S. degree in electrical engineering from University of Illinois Urbana-Champaign (UIUC), Urbana, IL,USA, in 2019. He is currently pursuing the Ph.D. degree in electrical engineering with UIUC. His research interests include ESD, device physics, compact modeling, and TCAD.
Author's Corner for 1A.1 and 1A.2
1A.3 A Physics-Based Model for ESD Protection Devices with Open Base BJT Configuration
![Seyed Mostafa Mousavi](/assets/Presenters/Seyed-Mostafa-Mousavi__FillMaxWzYwMCw2MDBd.jpg)
Seyed Mostafa Mousavi
Seyed Mostafa Mousavi (Senior Member, IEEE) received the B.Sc. degree from the Iran University of Sci. and Tech., Tehran, Iran, in 2007, and the M.Sc. and Ph.D. degrees from the K.N. Toosi University of Tech., Tehran, Iran, in 2010 and 2016, respectively, all in electrical engineering. In 2022, he joined Graz University of Technology, Graz, Austria before moving to the EMC Lab, Missouri University S&T, Rolla, MO, USA, where he is currently a Postdoctoral Fellow, specializing in EMC, ESD, and signal integrity.
1A.3 A Physics-Based Model for ESD Protection Devices with Open Base BJT Configuration
1A.4 Substrate NPN Extraction from Capacitance Field Solver
![Chuan Xu](/assets/Presenters/Chuan-Xu__FillMaxWzYwMCw2MDBd.png)
Chuan Xu
Dr. Chuan Xu received the B.S. and the M.S. from Peking University. He received the Ph.D. from University of California at Santa Barbara in 2012. During his Ph.D. program, he interned with IBM T. J. Watson Research Center and Mentor Graphics Corporation. In 2012, he joined the Device Modeling Team of Legacy Maxim Integrated (acquired by Analog Devices since 2021). His current research interests include modeling of active devices, parasitic devices, interconnects and packages in VLSI circuits. He has authored or co-authored over 40 journal and conference papers.
1A.4 Substrate NPN Extraction from Capacitance Field Solver
1A.5 An Efficient and Cost-effective Method to Detect and Analyze ESD CDM Risks in Designs
![Subhadeep Ghosh](/assets/Presenters/Subhadeep-Ghosh__FillMaxWzYwMCw2MDBd.jpg)
Subhadeep Ghosh
Subhadeep Ghosh received his Bachelor's Degree in Electronics from Jadavpur University, Kolkata, India, and Masters Degree in Electronics from Indian Institute of Technology, Kharagpur, India. He joined Texas Instruments in Bangalore, India in 2005 and has since worked on Reliability EDA development for EMIR analysis, Transistor reliability and ESD. Currently he leads the EDA Development for Reliability, ESD and IR-drop analyses for all TI internal process nodes. He is a Member, Group Technical Staff (MGTS). His areas of expertise are design reliability, ESD EDA, digital design IR-drop, with methods enabling reliability as a specification through the design flow.
1A.5 An Efficient and Cost-effective Method to Detect and Analyze ESD CDM Risks in Designs
Authors Corner for 1A.3, 1A.4, and 1A.5
![Subhadeep Ghosh](/assets/Presenters/Subhadeep-Ghosh__FillMaxWzYwMCw2MDBd.jpg)
Subhadeep Ghosh
Subhadeep Ghosh received his Bachelor's Degree in Electronics from Jadavpur University, Kolkata, India, and Masters Degree in Electronics from Indian Institute of Technology, Kharagpur, India. He joined Texas Instruments in Bangalore, India in 2005 and has since worked on Reliability EDA development for EMIR analysis, Transistor reliability and ESD. Currently he leads the EDA Development for Reliability, ESD and IR-drop analyses for all TI internal process nodes. He is a Member, Group Technical Staff (MGTS). His areas of expertise are design reliability, ESD EDA, digital design IR-drop, with methods enabling reliability as a specification through the design flow.
![Seyed Mostafa Mousavi](/assets/Presenters/Seyed-Mostafa-Mousavi__FillMaxWzYwMCw2MDBd.jpg)
Seyed Mostafa Mousavi
Seyed Mostafa Mousavi (Senior Member, IEEE) received the B.Sc. degree from the Iran University of Sci. and Tech., Tehran, Iran, in 2007, and the M.Sc. and Ph.D. degrees from the K.N. Toosi University of Tech., Tehran, Iran, in 2010 and 2016, respectively, all in electrical engineering. In 2022, he joined Graz University of Technology, Graz, Austria before moving to the EMC Lab, Missouri University S&T, Rolla, MO, USA, where he is currently a Postdoctoral Fellow, specializing in EMC, ESD, and signal integrity.
![Chuan Xu](/assets/Presenters/Chuan-Xu__FillMaxWzYwMCw2MDBd.png)
Chuan Xu
Dr. Chuan Xu received the B.S. and the M.S. from Peking University. He received the Ph.D. from University of California at Santa Barbara in 2012. During his Ph.D. program, he interned with IBM T. J. Watson Research Center and Mentor Graphics Corporation. In 2012, he joined the Device Modeling Team of Legacy Maxim Integrated (acquired by Analog Devices since 2021). His current research interests include modeling of active devices, parasitic devices, interconnects and packages in VLSI circuits. He has authored or co-authored over 40 journal and conference papers.
Authors Corner for 1A.3, 1A.4, and 1A.5
Tuesday, September 17
Morning Welcome
Morning Welcome
Keynote - Charting a Connected Future
![Daniel Cooley](/assets/Presenters/Daniel-Cooley-Headshot__FillMaxWzYwMCw2MDBd.jpg)
Daniel Cooley
Daniel Cooley serves as Chief Technology Officer and Senior Vice President, Technology and Product Development, where he is responsible for the company’s overall research and development strategy and execution. Cooley is a respected IoT industry veteran and has been instrumental in building the unmatched breadth and depth of the company’s wireless connectivity portfolio. Previously, Daniel served as Senior Vice President and Chief Strategy Officer, where he led Silicon Labs’ overall strategy, corporate development, M&A, emerging markets, and security. Prior to that, Daniel led Silicon Labs’ IoT business as Senior Vice President and General Manager. Since 2005, Cooley has served in a variety of engineering and business leadership positions at Silicon Labs in the US, Asia and Europe. He has an M.S. in Electrical Engineering from Stanford University and a B.S. in Electrical Engineering from The University of Texas at Austin and holds five patents in radio and low-power technology. Daniel currently serves on the board of directors for the Cockrell School of Engineering Advisory Board and the Austin Symphony Orchestra.
Keynote - Charting a Connected Future
2A.1 ESD Behavior of RF Switches and Importance of System Efficient ESD Design (EMC+SIPI Exchange Paper)
![Seyed Mostafa Mousavi](/assets/Presenters/Seyed-Mostafa-Mousavi__FillMaxWzYwMCw2MDBd.jpg)
Seyed Mostafa Mousavi
Seyed Mostafa Mousavi (Senior Member, IEEE) received the B.Sc. degree from the Iran University of Sci. and Tech., Tehran, Iran, in 2007, and the M.Sc. and Ph.D. degrees from the K.N. Toosi University of Tech., Tehran, Iran, in 2010 and 2016, respectively, all in electrical engineering. In 2022, he joined Graz University of Technology, Graz, Austria before moving to the EMC Lab, Missouri University S&T, Rolla, MO, USA, where he is currently a Postdoctoral Fellow, specializing in EMC, ESD, and signal integrity.
2A.1 ESD Behavior of RF Switches and Importance of System Efficient ESD Design (EMC+SIPI Exchange Paper)
2A.2 On-Chip ESD Protection for Multi-Gbps Automotive Serial IO in a 16-nm FinFET Process
![Shudong Huang](/assets/Presenters/Shudong-Huang-v2__FillMaxWzYwMCw2MDBd.jpg)
Shudong Huang
Shudong Huang is a Ph.D. student in the Department of Electrical and Computer Engineering at the University of Illinois Urbana-Champaign. His research interests include the design of broadband ESD protection devices and circuits for high-speed wireline circuits and RFIC in advanced CMOS technologies and compact modeling of ESD devices.
2A.2 On-Chip ESD Protection for Multi-Gbps Automotive Serial IO in a 16-nm FinFET Process
2A.3 Influence of TVS Properties and Printed Circuit Board Design on System Level ESD Robustness for USB-C SuperSpeed Data Lines
![Steffen Holland](/assets/Presenters/Steffen-Holland-v3__FillMaxWzYwMCw2MDBd.jpg)
Steffen Holland
Steffen Holland received his diploma and PhD in Physics from the University of Hamburg in 2004. He joined Philips Semiconductors/NXP/Nexperia in the process development group for discrete bipolar devices in Hamburg, Germany in 2005. The main focus of his work quickly became TCAD process and device simulations for discrete ESD protection devices. He works now on discrete ESD protection devices. His current interests are system level ESD simulations. He currently serves in the Board of Directors at the ESD Association and is chair of the ESDA working group 26.
2A.3 Influence of TVS Properties and Printed Circuit Board Design on System Level ESD Robustness for USB-C SuperSpeed Data Lines
Authors Corner for 2A.1, 2A.2, and 2A.3
![Steffen Holland](/assets/Presenters/Steffen-Holland-v3__FillMaxWzYwMCw2MDBd.jpg)
Steffen Holland
Steffen Holland received his diploma and PhD in Physics from the University of Hamburg in 2004. He joined Philips Semiconductors/NXP/Nexperia in the process development group for discrete bipolar devices in Hamburg, Germany in 2005. The main focus of his work quickly became TCAD process and device simulations for discrete ESD protection devices. He works now on discrete ESD protection devices. His current interests are system level ESD simulations. He currently serves in the Board of Directors at the ESD Association and is chair of the ESDA working group 26.
![Shudong Huang](/assets/Presenters/Shudong-Huang-v2__FillMaxWzYwMCw2MDBd.jpg)
Shudong Huang
Shudong Huang is a Ph.D. student in the Department of Electrical and Computer Engineering at the University of Illinois Urbana-Champaign. His research interests include the design of broadband ESD protection devices and circuits for high-speed wireline circuits and RFIC in advanced CMOS technologies and compact modeling of ESD devices.
![Seyed Mostafa Mousavi](/assets/Presenters/Seyed-Mostafa-Mousavi__FillMaxWzYwMCw2MDBd.jpg)
Seyed Mostafa Mousavi
Seyed Mostafa Mousavi (Senior Member, IEEE) received the B.Sc. degree from the Iran University of Sci. and Tech., Tehran, Iran, in 2007, and the M.Sc. and Ph.D. degrees from the K.N. Toosi University of Tech., Tehran, Iran, in 2010 and 2016, respectively, all in electrical engineering. In 2022, he joined Graz University of Technology, Graz, Austria before moving to the EMC Lab, Missouri University S&T, Rolla, MO, USA, where he is currently a Postdoctoral Fellow, specializing in EMC, ESD, and signal integrity.
Authors Corner for 2A.1, 2A.2, and 2A.3
EMC Invited Talk - Challenges in USBC ESD Protection
![Ketan Shringarpure](/assets/Presenters/Ketan-Shringarpure__FillMaxWzYwMCw2MDBd.jpg)
Ketan Shringarpure
Ketan Shringarpure completed his MS and PhD from Missouri S&T EMCLAB in 2015. He joined the industry as an EMC design engineer, now at Google for the last 7 years. His research interests include EM emissions and interference, and, ESD protection design and characterization.
EMC Invited Talk - Challenges in USBC ESD Protection
System Level Workshop - Automotive System Level ESD Protection Design in the Times of Multi-Gigabit Data Rates
![Steffen Holland](/assets/Presenters/Steffen-Holland-v3__FillMaxWzYwMCw2MDBd.jpg)
Steffen Holland
Steffen Holland received his diploma and PhD in Physics from the University of Hamburg in 2004. He joined Philips Semiconductors/NXP/Nexperia in the process development group for discrete bipolar devices in Hamburg, Germany in 2005. The main focus of his work quickly became TCAD process and device simulations for discrete ESD protection devices. He works now on discrete ESD protection devices. His current interests are system level ESD simulations. He currently serves in the Board of Directors at the ESD Association and is chair of the ESDA working group 26.
![Peter Koeppen](/assets/Presenters/Peter-Koeppen__FillMaxWzYwMCw2MDBd.jpg)
Peter Koeppen
Peter Koeppen is an ESD consultant in the electrical and electronic design and manufacturing industry focusing on semiconductors, ESD design and debugging for analog and digital circuit design, integrated circuits (IC), and CMOS.
System Level Workshop - Automotive System Level ESD Protection Design in the Times of Multi-Gigabit Data Rates
EMC Invited Talk (with Paper) - Extending ESD Network Capability to EOS and Overvoltage Protection
![Vladislav Vashchenko](/assets/Presenters/Vladislav-Vashchenko-v3__FillMaxWzYwMCw2MDBd.jpg)
Vladislav Vashchenko
Dr. Vladislav Vashchenko is currently Sr. Director Power ESD Group at Analog Devices Corp since 2011. He is responsible for aspects of power analog ESD/Latchup IC co-design business process and technology development. Previously he managed ESD technology development at National Semiconductor (2000-2011). He received MS Engineer-Physicist (1987), Ph.D. in Physics of Semiconductors from MIPT (1990), "Doctor of Science in Microelectronics" habilitation degree (1997). He is author of 150 U.S. patents, over 120 papers, co-author of the three books in ESD field.
EMC Invited Talk (with Paper) - Extending ESD Network Capability to EOS and Overvoltage Protection
3A.1 ESD Robustness of Germanium Photodetectors in Advanced Silicon Photonics Technology
![Kateryna Serbulova](/assets/Presenters/Kateryna-Serbulova-v3__FillMaxWzYwMCw2MDBd.jpg)
Kateryna Serbulova
Kateryna Serbulova received B.Sc. and M.Sc. in Micro- and Nano-system technology from National Technical University of Ukraine "Igor Sikorsky Kyiv Polytechnic Institute", Ukraine in 2017 and 2019 respectively. She joined department of electrical engineering ESAT, KU Leuven, Belgium and Device Reliability and Electrical Characterization group in imec, Belgium as a PhD student in 2019. Her current research topic focuses on transient-induced latch-up exploration in System-Technology-Co-Optimization scaling era.
3A.1 ESD Robustness of Germanium Photodetectors in Advanced Silicon Photonics Technology
3A.2 ESD-EOS-OVP Protection Network for Battery Pins
![Vladislav Vashchenko](/assets/Presenters/Vladislav-Vashchenko-v3__FillMaxWzYwMCw2MDBd.jpg)
Vladislav Vashchenko
Dr. Vladislav Vashchenko is currently Sr. Director Power ESD Group at Analog Devices Corp since 2011. He is responsible for aspects of power analog ESD/Latchup IC co-design business process and technology development. Previously he managed ESD technology development at National Semiconductor (2000-2011). He received MS Engineer-Physicist (1987), Ph.D. in Physics of Semiconductors from MIPT (1990), "Doctor of Science in Microelectronics" habilitation degree (1997). He is author of 150 U.S. patents, over 120 papers, co-author of the three books in ESD field.
3A.2 ESD-EOS-OVP Protection Network for Battery Pins
3A.3 Bidirectional DIAC Devices with Two-Stage Triggering
![Michael Amato](/assets/Presenters/Michael-Amato__FillMaxWzYwMCw2MDBd.jpg)
Michael Amato
Michael Amato graduated from Rensselaer Polytechnic Institute with a BSEE in ‘82 and MSEE in '84, with emphasis in semiconductor device and IC technology. At Philips Research he led teams developing new monolithic Power IC technologies and TFT arrays for LCD HDTV. Working at Allegro Microsystems & CPClare (IXYS), he also directed CAD/PDK development and device modeling. In 2004 he joined Linear Technology Corp (now Analog Devices Inc) directing all ESD Co-design and new ESD device development for in-house and foundry processes, developing unique ESD solutions for High Voltage, Power, Analog, Digital, and Mixed Signal ICs.
3A.3 Bidirectional DIAC Devices with Two-Stage Triggering
Authors Corner for 3A.1, 3A.2, and 3A.3
![Michael Amato](/assets/Presenters/Michael-Amato__FillMaxWzYwMCw2MDBd.jpg)
Michael Amato
Michael Amato graduated from Rensselaer Polytechnic Institute with a BSEE in ‘82 and MSEE in '84, with emphasis in semiconductor device and IC technology. At Philips Research he led teams developing new monolithic Power IC technologies and TFT arrays for LCD HDTV. Working at Allegro Microsystems & CPClare (IXYS), he also directed CAD/PDK development and device modeling. In 2004 he joined Linear Technology Corp (now Analog Devices Inc) directing all ESD Co-design and new ESD device development for in-house and foundry processes, developing unique ESD solutions for High Voltage, Power, Analog, Digital, and Mixed Signal ICs.
![Vladislav Vashchenko](/assets/Presenters/Vladislav-Vashchenko-v3__FillMaxWzYwMCw2MDBd.jpg)
Vladislav Vashchenko
Dr. Vladislav Vashchenko is currently Sr. Director Power ESD Group at Analog Devices Corp since 2011. He is responsible for aspects of power analog ESD/Latchup IC co-design business process and technology development. Previously he managed ESD technology development at National Semiconductor (2000-2011). He received MS Engineer-Physicist (1987), Ph.D. in Physics of Semiconductors from MIPT (1990), "Doctor of Science in Microelectronics" habilitation degree (1997). He is author of 150 U.S. patents, over 120 papers, co-author of the three books in ESD field.
![Kateryna Serbulova](/assets/Presenters/Kateryna-Serbulova-v3__FillMaxWzYwMCw2MDBd.jpg)
Kateryna Serbulova
Kateryna Serbulova received B.Sc. and M.Sc. in Micro- and Nano-system technology from National Technical University of Ukraine "Igor Sikorsky Kyiv Polytechnic Institute", Ukraine in 2017 and 2019 respectively. She joined department of electrical engineering ESAT, KU Leuven, Belgium and Device Reliability and Electrical Characterization group in imec, Belgium as a PhD student in 2019. Her current research topic focuses on transient-induced latch-up exploration in System-Technology-Co-Optimization scaling era.
Authors Corner for 3A.1, 3A.2, and 3A.3
Semiconductor Fab ESD/Electrostatic Attraction (ESA) Controls Discussion Group
![Larry Levit](/assets/Presenters/Larry-Levit-v2__FillMaxWzYwMCw2MDBd.jpg)
Larry Levit
Dr. Larry Levit provides a variety of ESD consulting services as LBL Scientific. He was Global ESD program Manager for Finisar Corporation and Chief Scientist for MKS, Ion Systems, He has over 20 years of experience in the field of ESD control. He is a NARTE Certified ESD Engineer. Levit has audited cleanrooms on three continents and is recognized as a problem solver. He has successfully devised solutions to manufacturing problems to reduce ESD yield loss, contamination issues and reticle damage. Before joining MKS, Ion Systems, Levit held technical rolls at LeCroy Corporation and Jandel Scientific Software. At LeCroy, he contributed to the instrumentation designs for 6 experiments which produced Nobel prizes in physics. Levit taught physics at CWRU, LSU, and at Napa Valley Community College. He is a senior member of the ESD Association, a senior member of the IEST and chairs the WG CC022 Working Group for IEST. Levit graduated from Case Institute of Technology, Cleveland, Ohio with a BS degree in physics with honors. He then went on to earn a Ph.D. in Experimental High Energy Physics from Case Western Reserve University.
Andrew Nold
Andy Nold is a Quality Engineer and Commodity Engineer at Teradyne near Chicago, IL. He is the Factory ESD subject matter expert and performs the company’s internal ESD audits. He has worked for Teradyne since 2011.
Prior to Teradyne, Andy worked for the FAA, a small aerospace company, and the US Navy. Andy graduated from the University of Wisconsin with a bachelor’s degree in Applied Math, Engineering, and Physics and a master’s degree in Engineering Mechanics.
Outside of work, Andy likes to spend time with his wife and kids.
Semiconductor Fab ESD/Electrostatic Attraction (ESA) Controls Discussion Group
Wednesday, September 18
Morning Welcome
Morning Welcome
Keynote - Advanced Failure Analysis Techniques and Workflows for 3D Packaged Devices
![Frank Altman](/assets/Presenters/Altmann-Frank-Kopie__FillMaxWzYwMCw2MDBd.jpg)
Frank Altman
Frank Altmann received his Diploma in Physics from the Technical University, Dresden. He joined the Fraunhofer IWM (now IMWS) in 1997 and has since been concerned with material diagnostics and failure analysis of semiconductor components. Since 2006, he has been head of the research group Diagnostics of Semiconductor Technologies, with responsibility for national and international research projects with industry and public organizations focusing on 3D packaging and Si and GaN chip technologies. Since 2019, he has been acting head of the department of Electronic Materials and Components. Frank Altmann has authored and co-authored more than 130 publications, is active within several national and international failure analysis conferences and education committees, and was the general chair of ISTFA 2023.
Keynote - Advanced Failure Analysis Techniques and Workflows for 3D Packaged Devices
4A.1 Transistor Layout and Technology Impacts on ESD HBM Performance of GaN-on-SiC RF HEMTs
![Wei-Min Wu](/assets/Presenters/Wei-Min-Wu__FillMaxWzYwMCw2MDBd.jpg)
Wei-Min Wu
Wei-Min Wu received the dual-Ph.D. degrees in electrical engineering from the KU Leuven, Belgium, and in electronic engineering from National Yang Ming Chiao Tung University (NYCU), Taiwan in 2022. He is now with IMEC, Leuven, Belgium as an RF ESD researcher. His current research interests include ESD protections in Design Technology Co-Optimization (DTCO) with the Si/III-V RF devices and circuits and in high-speed I/O technology.
4A.1 Transistor Layout and Technology Impacts on ESD HBM Performance of GaN-on-SiC RF HEMTs
4A.2 ESD Protection Analysis for 3D NAND Internal Source Plate Discharge Circuit
![James Davis](/assets/Presenters/James-Davis__FillMaxWzYwMCw2MDBd.jpg)
James Davis
James Davis received a B.S. degree in electrical engineering from Brigham Young University (Provo, Utah USA) in 2002. He has been involved with on-chip ESD protection at Micron Technology, Inc. (Boise, Idaho USA) for the past twenty years. He is currently part of the R&D group focusing on on-chip ESD protection and design for NAND flash products. Mr. Davis is currently a Senior Member Technical Staff ESD/Latchup engineer.
4A.2 ESD Protection Analysis for 3D NAND Internal Source Plate Discharge Circuit
4A.3 Efficient Pre-Silicon ESD Verification for Enabling High Performance IO Design
![Priya Walimbe](/assets/Presenters/Priya-Walimbe__FillMaxWzYwMCw2MDBd.png)
Priya Walimbe
Priya Walimbe has a master's degree in EE wand 25 years of experience in High Speed IO and Analog design. Currently, she is a Principal Engineer at Intel, providing technical leadership for innovations in state-of-the-art IO design and methodologies. She one of the leaders in architecture and design of several generations of DDR/LPDDR PHYs. She has heavily contributed to design technology co-optimization on Intel internal and external foundry. Priya has been an active member of ESD community at Intel, leading ESD design and verification improvements and innovations. She holds 6 patents, authored/co-authored many publications. She's art loving and enjoys classical music.
4A.3 Efficient Pre-Silicon ESD Verification for Enabling High Performance IO Design
Authors Corner for 4A.1, 4A.2, and 4A.3
![James Davis](/assets/Presenters/James-Davis__FillMaxWzYwMCw2MDBd.jpg)
James Davis
James Davis received a B.S. degree in electrical engineering from Brigham Young University (Provo, Utah USA) in 2002. He has been involved with on-chip ESD protection at Micron Technology, Inc. (Boise, Idaho USA) for the past twenty years. He is currently part of the R&D group focusing on on-chip ESD protection and design for NAND flash products. Mr. Davis is currently a Senior Member Technical Staff ESD/Latchup engineer.
![Priya Walimbe](/assets/Presenters/Priya-Walimbe__FillMaxWzYwMCw2MDBd.png)
Priya Walimbe
Priya Walimbe has a master's degree in EE wand 25 years of experience in High Speed IO and Analog design. Currently, she is a Principal Engineer at Intel, providing technical leadership for innovations in state-of-the-art IO design and methodologies. She one of the leaders in architecture and design of several generations of DDR/LPDDR PHYs. She has heavily contributed to design technology co-optimization on Intel internal and external foundry. Priya has been an active member of ESD community at Intel, leading ESD design and verification improvements and innovations. She holds 6 patents, authored/co-authored many publications. She's art loving and enjoys classical music.
![Wei-Min Wu](/assets/Presenters/Wei-Min-Wu__FillMaxWzYwMCw2MDBd.jpg)
Wei-Min Wu
Wei-Min Wu received the dual-Ph.D. degrees in electrical engineering from the KU Leuven, Belgium, and in electronic engineering from National Yang Ming Chiao Tung University (NYCU), Taiwan in 2022. He is now with IMEC, Leuven, Belgium as an RF ESD researcher. His current research interests include ESD protections in Design Technology Co-Optimization (DTCO) with the Si/III-V RF devices and circuits and in high-speed I/O technology.
Authors Corner for 4A.1, 4A.2, and 4A.3
Network in the Exhibit Hall with the Exhibitors and Your Fellow Attendees
![Alfred J. Griffin, Jr.](/assets/Presenters/Alfred-J__FillMaxWzYwMCw2MDBd.-Griffin-Jr..jpg)
Alfred J. Griffin, Jr.
Al Griffin joined Texas Instruments, Inc. in 1996, and was elected Senior Fellow in February 2020. He has over 30 years of experience in metallurgy, materials science, materials reliability and materials integration, particularly with respect to semiconductor and printed circuit board manufacturing. Al Griffin manages some of TI’s most critical customer return, excursion and qualification issues across all of TI’s technologies and factories and is a founding member of The Red Team, a problem-solving organization. He has worked with most of TI’s top engineers, designers and customers and has collaborated across TI to solve customers’ problems and a wide range of worldwide TI wafer fab and AT issues. Al received his B.S. in Metallurgical Engineering from the University of Texas at El Paso and his Ph.D. and M.S. in Materials Science from Rice University.
Network in the Exhibit Hall with the Exhibitors and Your Fellow Attendees
Circuit Design Workshop - Design Challenges Due to Ultra-Short Voltage Stress Pulses in Advanced Technologies
![Michael Stockinger](/assets/Presenters/Michi-Stockinger-v3__FillMaxWzYwMCw2MDBd.jpg)
Michael Stockinger
Michael “Michi” Stockinger received his PhD in electrical engineering with highest honors from Vienna University, Austria, in 2000. His doctoral research focused on the optimization of ultra-low-power CMOS transistors. In 2000, he moved to Austin, Texas to join Motorola’s semiconductor sector, which became Freescale Semiconductor in 2004 and then NXP Semiconductors in 2016. Michael’s focus has been on ESD protection and LU prevention for advanced CMOS products. He is a Technical Director of ESD design in NXP’s MCU/MPU Engineering division. Michael’s on-chip ESD solutions have been implemented in the Kinetis, i.MX, and ColdFire product lines. Michael was awarded several EOS/ESD Symposium awards: 2001 Best Paper, 2003 Best Paper and Best Presentation, 2013 Best Paper and Outstanding Paper, and 2020 Best Paper. He has authored over 40 technical papers and holds 30 patents. He has served in the TPC of several EOS/ESD Symposia, International Reliability and Physics Symposia, and International ESD Workshops, and he teaches an ESDA tutorial.
![David Johnsson](/assets/Presenters/David-Johnsson__FillMaxWzYwMCw2MDBd.jpg)
David Johnsson
Circuit Design Workshop - Design Challenges Due to Ultra-Short Voltage Stress Pulses in Advanced Technologies
Emerging Technologies Invited Talk - Toward a Trillion Transistors - ESD Perspectives on Emerging IC Technologies
![Marko Simicic](/assets/Presenters/Marko-Simicic-v3__FillMaxWzYwMCw2MDBd.jpg)
Marko Simicic
Marko Simicic received the M.Sc. degree in electrical engineering and information technology from the University of Zagreb, Croatia, in 2012. He obtained a PhD degree from the department of electrical engineering ESAT, KU Leuven, Belgium in 2018. Since 2017 he is an ESD researcher in imec, Belgium. He is a certified ESD control program manager since 2022. He has authored or co-authored more than 40 papers in international journals and conference proceedings. His current research area is rather wide and includes ESD device and circuit design in advanced semiconductor and 3D/2.5D stacking technologies, novel ESD testing and ESD control process assessment.
Emerging Technologies Invited Talk - Toward a Trillion Transistors - ESD Perspectives on Emerging IC Technologies
Emerging Technologies Invited Talk - Transforming Power Electronics: An Overview of SiC Technology and its Applications
![Kiran Chatty](/assets/Presenters/Kiran-Chaty-BW__FillMaxWzYwMCw2MDBd.jpg)
Kiran Chatty
Kiran Chatty is the Senior Director of SiC Products at Alpha & Omega Semiconductor (AOS) Inc., a leading power semiconductor company based in Sunnyvale, CA. Prior to joining AOS, he co-founded Monolith Semiconductor Inc., a startup focused on developing SiC MOSFETs and Schottky Diodes for power electronic applications. Monolith Semiconductor was acquired by Littelfuse Inc., in 2018, where he served as the Director of SiC Product Development. Kiran started his career in 2000 at IBM’s Semiconductor Research & Development Center in Burlington VT working on ESD & Latchup technology development. Over the next decade, he worked on developing ESD protection devices & strategies in advanced CMOS, analog mixed signal & high voltage technologies. Kiran has served as member, chair or co-chair of several conferences including EOS/ESD Symposium. He has been granted over 60 issued patents and published over 50 papers in ESD, Latchup & SiC high voltage technology.
Emerging Technologies Invited Talk - Transforming Power Electronics: An Overview of SiC Technology and its Applications
Networking Break
Networking Break
5A.1 TDDB of Sensitive High-K Gate Dielectrics – Revisited for CDM
![Mirko Scholz](/assets/Presenters/Mirko-Scholz-v2__FillMaxWzYwMCw2MDBd.png)
Mirko Scholz
Dr. Mirko Scholz received his Ph.D. in Electrical Engineering from the Vrije Universiteit in Brussels (VUB) in 2013. From 2005 until 2017, he was working as an ESD researcher at imec in Leuven/Belgium. From March 2017 until June 2019, he was a program manager at the imec academy and in imec’s process technology transfer activities. Since July 2019, he has been with Infineon Technologies in Munich/Germany, where he is a Principal Engineer in ESD Development. His daily work focuses on component- and system-level ESD protection design for several RF and sensor product lines at Infineon.
Since 2007 he has been an active member of different working groups in the ESDA standards committee, currently co-chairing WG 5.6 (Human Metal Model). He was the management chair of the IEW 2018 in Belgium. Since 2019 he has been a member of the steering committee of the EOS/ESD Symposium. In this function, he is the Technical Program Committee (TPC) chair of the EOS/ESD Symposium 2023. For the 2017-2019 term and again for the 2022-2024 term, he has been an elected member of the ESDA Board of Directors. Since 2017, he has been heading the business unit of the Advanced Topics Committee of the ESDA.
He has authored/co-authored more than 100 publications, tutorials, and patents in the field of ESD design and testing. He is co-author of the 2014 Springer book “System-level ESD Protection”. He is a regular reviewer for several IEEE journals and a current member of the IRPS sub-committee on ESD and Latchup.
5A.1 TDDB of Sensitive High-K Gate Dielectrics – Revisited for CDM
5A.2 Self-Sufficient ESD Solution for Fail-safe I/O Design in FinFET Technology
![Hsin-Yu Chen](/assets/Presenters/Hsin-Yu-Chen__FillMaxWzYwMCw2MDBd.jpg)
Hsin-Yu Chen
Hsin-Yu Chen received the B.S. degree from the Department of Applied Physics, National University of Kaohsiung, Kaohsiung, Taiwan, in 2016, and the M.S. degree from the Institute of Electrophysics, National Chiao-Tung University, Hsinchu, Taiwan, in 2019. She joined Taiwan Semiconductor Manufacturing Company (TSMC) in 2019 and she is in ESD/EOS Technology Department.
5A.2 Self-Sufficient ESD Solution for Fail-safe I/O Design in FinFET Technology
5A.3 Single Event Latch-up (SEL) Rate Prediction Methodology in Bulk FinFET Technology
![Tzu-Hao Chiang](/assets/Presenters/Tzu-Hao-Chiang__FillMaxWzYwMCw2MDBd.jpg)
Tzu-Hao Chiang
Tzu-Hao Chiang received the B.S. degree in electrical engineering and the M.S. degree in electronic engineering from National Taiwan University, Taipei, Taiwan, in 2020. He joined Taiwan Semiconductor Manufacturing Company (TSMC) in 2020, where he is currently a Senior Engineer in ESD/EOS Technology Department. His work is mainly on single event latchup (SEL) and ESD victim design solution development.
5A.3 Single Event Latch-up (SEL) Rate Prediction Methodology in Bulk FinFET Technology
Authors Corner for 5A.1, 5A.2, and 5A.3
![Hsin-Yu Chen](/assets/Presenters/Hsin-Yu-Chen__FillMaxWzYwMCw2MDBd.jpg)
Hsin-Yu Chen
Hsin-Yu Chen received the B.S. degree from the Department of Applied Physics, National University of Kaohsiung, Kaohsiung, Taiwan, in 2016, and the M.S. degree from the Institute of Electrophysics, National Chiao-Tung University, Hsinchu, Taiwan, in 2019. She joined Taiwan Semiconductor Manufacturing Company (TSMC) in 2019 and she is in ESD/EOS Technology Department.
![Tzu-Hao Chiang](/assets/Presenters/Tzu-Hao-Chiang__FillMaxWzYwMCw2MDBd.jpg)
Tzu-Hao Chiang
Tzu-Hao Chiang received the B.S. degree in electrical engineering and the M.S. degree in electronic engineering from National Taiwan University, Taipei, Taiwan, in 2020. He joined Taiwan Semiconductor Manufacturing Company (TSMC) in 2020, where he is currently a Senior Engineer in ESD/EOS Technology Department. His work is mainly on single event latchup (SEL) and ESD victim design solution development.
![Christian C. Russ](/assets/Presenters/Christian-Russ__FillMaxWzYwMCw2MDBd.jpg)
Christian C. Russ
Dr. Christian Russ received his MS and PhD degrees in electrical engineering from the Technical University of Munich, Germany, in 1991 and 1999, respectively. He has spent more than 30 years in the field of ESD: from 1994 through 1998, he was with IMEC, Leuven, Belgium, and from 1998 through 2003 he worked for Sarnoff Corporation, Princeton, New Jersey, USA. In 2003, he joined Infineon Technologies, Munich, Germany. In 2011, he transferred to Intel Mobile Communications where he developed ESD concepts for planar and FinFET CMOS technologies. Since 2017, he has been at Infineon Technologies as lead principal engineer for ESD solutions in automotive sensor technologies (Smart Power, CMOS, BiCMOS). Christian was recipient of several Best Paper Awards at the EOS/ESD Symposia (1993, 1996, 1998, 2000, 2001, 2005, 2012 and 2021) and at the ESREF Conference (1993, 1995). He has published over 75 conference and journal publications and has been awarded over 80 patents in his field.