Saturday, September 14
Introduction to On-Chip ESD Protection
Oliver Marichal
Olivier Marichal graduated from Katholieke Universiteit Leuven with a degree in Electrical Engineering in 2003 and has since dedicated his career to the field of Electrostatic Discharge (ESD) protection design, currently serving as Chief Engineering at Sofics. His journey with the company began shortly after graduation as an ESD engineer, and over the years, Olivier has worked on many projects, covering a broad range of technologies from High Voltage BCD to the latest nanometer Finfet processes. His professional focus is on continuously adding value to customers through his work, delivering state-of-the-art ESD solutions for the ever-evolving landscape of semiconductor applications.
Olivier has (co-)authored several papers on ESD and contributed as an inventor on many patents. In addition to his technical contributions, Olivier is dedicated to sharing his knowledge and insights. He has conducted several tutorials on on-chip ESD protection design for industry professionals around the world.
Introduction to On-Chip ESD Protection
Sunday, September 15
Introduction to Characterization of On-Chip ESD Protection
Wim Vanhouteghem
Wim Vanhouteghem is a Senior ESD Design Engineer and the head of the measurement lab at Sofics. A 2007 graduate of KHBO (now part of the Catholic University of Leuven), Wim joined Sofics immediately after completing his studies. His work primarily focuses on ESD protection in semiconductor technologies, ranging from high-voltage BCD to FinFETs.
Wim has plenty of experience in implementing ESD protection and conducting ESD measurements. He contributed to the SEED concept and has worked on system-level ESD measurements on bare dies.
Introduction to Characterization of On-Chip ESD Protection
Overview on ESD and Latch-up Challenges in 2.5D and 3D-Stacked ICs
Mirko Scholz
Dr. Mirko Scholz received his Ph.D. in Electrical Engineering from the Vrije Universiteit in Brussels (VUB) in 2013. From 2005 until 2017, he was working as an ESD researcher at imec in Leuven/Belgium. From March 2017 until June 2019, he was a program manager at the imec academy and in imec’s process technology transfer activities. Since July 2019, he has been with Infineon Technologies in Munich/Germany, where he is a Principal Engineer in ESD Development. His daily work focuses on component- and system-level ESD protection design for several RF and sensor product lines at Infineon.
Since 2007 he has been an active member of different working groups in the ESDA standards committee, currently co-chairing WG 5.6 (Human Metal Model). He was the management chair of the IEW 2018 in Belgium. Since 2019 he has been a member of the steering committee of the EOS/ESD Symposium. In this function, he is the Technical Program Committee (TPC) chair of the EOS/ESD Symposium 2023. For the 2017-2019 term and again for the 2022-2024 term, he has been an elected member of the ESDA Board of Directors. Since 2017, he has been heading the business unit of the Advanced Topics Committee of the ESDA.
He has authored/co-authored more than 100 publications, tutorials, and patents in the field of ESD design and testing. He is co-author of the 2014 Springer book “System-level ESD Protection”. He is a regular reviewer for several IEEE journals and a current member of the IRPS sub-committee on ESD and Latchup.
Marko Simicic
Marko Simicic received the M.Sc. degree in electrical engineering and information technology from the University of Zagreb, Croatia, in 2012. He obtained a PhD degree from the department of electrical engineering ESAT, KU Leuven, Belgium in 2018. Since 2017 he is an ESD researcher in imec, Belgium. He is a certified ESD control program manager since 2022. He has authored or co-authored more than 40 papers in international journals and conference proceedings. His current research area is rather wide and includes ESD device and circuit design in advanced semiconductor and 3D/2.5D stacking technologies, novel ESD testing and ESD control process assessment.
Overview on ESD and Latch-up Challenges in 2.5D and 3D-Stacked ICs
ESD Design Challenges of RF and High Speed I/Os
Dolphin Abessolo-Bidzo
Dr. Ir. Dolphin Abessolo-Bidzo received his M.Sc. (2004) and his Ph.D. (2007) in Electrical Engineering from ENSICAEN and from the University of Basse-Normandie, France. He is currently working as Senior Principal RF ESD & Latch-Up Design Engineer for advanced RFCMOS and BiCMOS technologies of RF and Millimeter wave applications at NXP Semiconductors.
Dolphin has published numerous articles and papers in IEEE scientific journals, symposia, and conferences on ESD, RF, and time domain analysis and holds several patents in the field of ESD protection of integrated circuits (ICs).
He is an active member of the ESDA Workgroup-18 on Electronic Design Automation (EDA) for ESD. For more than 15 years, he has regularly served in the management and the technical program committees of the International Electrostatic Discharge Workshops (IEW’s) and the EOS/ESD Symposia. Dolphin was the Management Committee General Chair of the IEW2023 in Germany and is a 2024 member of the Board of Directors.