Agenda

The tutorial is designed to provide a comprehensive understanding of electrostatic discharge (ESD) events and its implications on semiconductor devices. The tutorial will delve into the fundamentals of ESD, including the physics behind the electrostatic build-up and discharge processes. Integrated circuits can get damaged by ESD events during manufacturing, testing or in assembly when they are handled by people or machines. IC layout engineers can influence the robustness of their circuits by applying guidelines and tricks. Participants will explore various ESD protection strategies and design methodologies used in modern integrated circuits (ICs). The material will cover ESD devices used from basic CMOS to advanced FinFET technologies. The session will cover key topics such as on-chip ESD protection device structures and layout considerations, Through a blend of theoretical knowledge and practical examples, the tutorial aims to equip attendees with the skills necessary to understand on-chip ESD protection schemes. This tutorial is ideal for IC engineers seeking to enhance their expertise in ESD protection for semiconductor devices.   

Abstract

This course is about characterizing the Electrostatic Discharge (ESD) robustness of semiconductor circuits and protection solutions. It includes the typical measurement techniques like HBM, MM, CDM, TLP, VF-TLP, HMM, and IEC 61000-4-2 used in the industry. The material provides an overview of the advantages and disadvantages of each technique.
 
The tutorial will also cover the interpretation of test results. Emphasis will be placed on understanding the trade-offs and design considerations in optimizing ESD protection devices for different applications.
 
This tutorial is tailored for professionals in semiconductor device design and testing, seeking to deepen their expertise in ESD characterization. 

Learning Outcomes

• Understanding ESD Characterization Techniques: Learn about the various techniques and methodologies used in the characterization of ESD protection devices.
• Familiarity with ESD Test Models: Learn about different ESD test models, such as Human Body Model (HBM), Machine Model (MM), and Charged Device Model (CDM), and their applications in device testing.
• Understand usage of Test Equipment: Understand the usage of specialized equipment for ESD characterisation, such as Transmission Line Pulse (TLP) testing systems.
• Interpreting Test Data: Develop the ability to analyze and interpret test results to assess the performance and reliability of ESD protection structures.

2.5D and 3D integration are commercially available packaging options in the semiconductor industry. The Industry Council on ESD targets level is working on a white paper that discusses the ESD challenges of die-to-die interfaces in 2.5D/3D stacked ICs. In this invited talk, we provide an overview of the ESD and latch-up challenges that are currently solved or need to be solved in the near future. We discuss the impact of 3D integration on the ESD and latch-up robustness. ESD testing challenges like the assessment of the CDM robustness of internal IOs are covered and the specific requirements for the ESD protection design in 2.5D/3D stacked ICs are discussed. Our talk will show that all ingredients for the successful enablement of commercial 2.5D/3D stacked ICs are ready to be used.

RF and high speed I/Os are typically very challenging to protect against ESD stresses. This is due to the very limited ESD protection capacitance load “budget” of those pins for functional reasons. Furthermore, as the advanced CMOS technology has evolved towards 5 nm FinFET and beyond, the thinner gate oxide makes the devices become more vulnerable to ESD zaps. At the same time, a trend of a 2X increase of per-pin data rate every 4 years is observed for high-speed SerDes wireline I/Os (e.g., USB, Ethernet, etc.), and higher bandwidth is required for RF I/Os of Millimeter wave Transceivers.
This presentation will cover the following topics:
•    The increase of data rate and bandwidth requirement for every SerDes generation and the advanced CMOS technology gate oxide scaling related aspects
•    The ESD design trade-offs and challenges of RF and High-Speed I/O’s
•    The examples of ESD design techniques applicable to RF and high-speed I/O’s (RF ESD co-design, T-coil design, etc.)
•    The lowering of CDM level for ultra-high-speed I/O interfaces (recommendation by the Industry Council on ESD Target Levels)

1. REGISTRATION

   To obtain certification, you must initiate an official file in your name at EOS/ESD Association, Inc. headquarters. Please complete the PDF registration form and send it with a $50 payment. Register Online

2. COMPLETE PREREQUISITE COURSES

   The courses are listed on our website at https://www.esda.org/certification/eosesd-association-professional-program-manager/. To view course abstracts, please visit https://www.esda.org/training-and-education/esda-tutorials/

3. PASS AN IN-DEPTH EXAMINATION

   The examination is held annually during the Symposium. The examination consists of multiple-choice and essay questions. Two individuals will grade the essay portion of the exam. The examination is open book. You may bring any reference materials, including, but not limited to, books, standards, and tutorial notes. You may also bring a calculator and computer. No cell phones, internet connections, or sharing of reference materials is allowed.

   Note: If passing criteria are not met for one or more sections, you will need to attend the applicable tutorials before retaking the exam.

4. COST

   To enroll in this program, there is an official registration filing fee of $50.00. An exam fee of $60 is applicable. Bundle price of $5,000 for all courses.

5. HOW DO I PAY?

   Purchase options for your organization:

   Issue a Corporate PO, receive Invoice from EOS/ESD Association, Inc., execute payment

   Individual - Complete personal purchase, receive a receipt, request invoice from EOS/ESD Association, Inc., submit to your company for reimbursement

   Bundle PO or Invoice  - Bundle multiple items for a corporate PO or purchase. Ask EOS/ESD Association, Inc. for an invoice for multiple attendees, memberships, standards, or any of our products or services to process one time inside your company.