Monday, September 16

8:00 AM
9:20 AM
9:30 AM

Invited Talk TBA

10:50 AM

Invited Talk TBA

11:40 AM
1:00 PM
1:50 PM
3:10 PM

1A.1 Accuracy Preserving Extensions to a PDK MOSFET Model for ESD Simulation

3:35 PM

1A.2 CDM ESD Risk Assessment for Ground-Crossing Circuit Through PERC P2P/CD Programming

4:00 PM

Author's Corner for 1A.1 and 1A.2

4:20 PM

1A.3 A Physics-Based Model for ESD Protection Devices with Open Base BJT Configuration

4:45 PM

1A.4 Substrate NPN Extraction from Capacitance Field Solver

5:10 PM

1A.5 An Efficient and Cost-effective Method to Detect and Analyze ESD CDM Risks in Designs

5:35 PM

Authors Corner for 1A.3, 1A.4, and 1A.5

Tuesday, September 17

8:00 AM
8:10 AM

KEYNOTE: Charting the Connected Future

9:45 AM

2A.1 ESD Behavior of RF Switches and Importance of System Efficient ESD Design (EMC+SIPI Exchange Paper)

10:10 AM

2A.2 On-Chip ESD Protection for Multi-Gbps Automotive Serial IO in a 16-nm FinFET Process

10:35 AM

2A.3 Influence of TVS Properties and Printed Circuit Board Design on System Level ESD Robustness for USB-C High-Speed Data Lines

11:00 AM

Authors Corner for 2A.1, 2A.2, and 2A.3

12:00 PM

EMC Invited Talk: TBA

3:35 PM

Photonics Invited Talk: TBA

4:55 PM

3A.1 ESD Robustness of Germanium Photodetectors in Advanced Silicon Photonics Technology

5:20 PM

3A.2 ESD-EOS-OVP Protection Network for Battery Pins

5:45 PM

3A.3 Bidirectional DIAC Devices with Two-Stage Triggering

6:10 PM

Authors Corner for 3A.1, 3A.2, and 3A.3

Wednesday, September 18

8:00 AM
8:10 AM

KEYNOTE: Advanced Failure Analysis Techniques and Workflows for 3D Packaged Devices

9:40 AM

4A.1 Transistor Layout and Technology Impacts on ESD HBM Performance of GaN-on-SiC RF HEMTs

10:05 AM

4A.2 ESD Protection Analysis for 3D NAND Internal Source Plate Discharge Circuit

10:30 AM

4A.3 Efficient Pre-Silicon ESD Verification for Enabling High Performance IO Design

10:55 AM

Authors Corner for 4A.1, 4A.2, and 4A.3

11:15 AM

Emerging Technologies Invited Talk: Root Cause Categories for Electrical Over-Stress (EOS) and Electrically Induced Physical Damage (EIPD) on Customer Returns and Qualification Failures

2:55 PM

Emerging Technologies Talk - Toward a Trillion Transistors - ESD Perspectives on Emerging IC Technologies

3:45 PM

Emerging Technologies Talk TBA

4:35 PM
4:55 PM

5A.1 TDDB of Sensitive Gate Dielectrics – Revisited for CDM

5:20 PM

5A.2 Self-Sufficient ESD Solution for Fail-safe I/O Design in FinFET Technology

5:45 PM

5A.3 Single Event Latch-up (SEL) Rate Prediction Methodology in Bulk FinFET Technology

6:10 PM

Authors Corner for 5A.1, 5A.2, and 5A.3