Wednesday, September 18
4A.1 Transistor Layout and Technology Impacts on ESD HBM Performance of GaN-on-SiC RF HEMTs
Wei-Min Wu
Wei-Min Wu received the dual-Ph.D. degrees in electrical engineering from the KU Leuven, Belgium, and in electronic engineering from National Yang Ming Chiao Tung University (NYCU), Taiwan in 2022. He is now with IMEC, Leuven, Belgium as an RF ESD researcher. His current research interests include ESD protections in Design Technology Co-Optimization (DTCO) with the Si/III-V RF devices and circuits and in high-speed I/O technology.
4A.1 Transistor Layout and Technology Impacts on ESD HBM Performance of GaN-on-SiC RF HEMTs
4A.2 ESD Protection Analysis for 3D NAND Internal Source Plate Discharge Circuit
James Davis
James Davis received a B.S. degree in electrical engineering from Brigham Young University (Provo, Utah USA) in 2002. He has been involved with on-chip ESD protection at Micron Technology, Inc. (Boise, Idaho USA) for the past twenty years. He is currently part of the R&D group focusing on on-chip ESD protection and design for NAND flash products. Mr. Davis is currently a Senior Member Technical Staff ESD/Latchup engineer.
4A.2 ESD Protection Analysis for 3D NAND Internal Source Plate Discharge Circuit
4A.3 Efficient Pre-Silicon ESD Verification for Enabling High Performance IO Design
Priya Walimbe
Priya Walimbe has a master's degree in EE wand 25 years of experience in High Speed IO and Analog design. Currently, she is a Principal Engineer at Intel, providing technical leadership for innovations in state-of-the-art IO design and methodologies. She one of the leaders in architecture and design of several generations of DDR/LPDDR PHYs. She has heavily contributed to design technology co-optimization on Intel internal and external foundry. Priya has been an active member of ESD community at Intel, leading ESD design and verification improvements and innovations. She holds 6 patents, authored/co-authored many publications. She's art loving and enjoys classical music.
4A.3 Efficient Pre-Silicon ESD Verification for Enabling High Performance IO Design
Authors Corner for 4A.1, 4A.2, and 4A.3
James Davis
James Davis received a B.S. degree in electrical engineering from Brigham Young University (Provo, Utah USA) in 2002. He has been involved with on-chip ESD protection at Micron Technology, Inc. (Boise, Idaho USA) for the past twenty years. He is currently part of the R&D group focusing on on-chip ESD protection and design for NAND flash products. Mr. Davis is currently a Senior Member Technical Staff ESD/Latchup engineer.
Priya Walimbe
Priya Walimbe has a master's degree in EE wand 25 years of experience in High Speed IO and Analog design. Currently, she is a Principal Engineer at Intel, providing technical leadership for innovations in state-of-the-art IO design and methodologies. She one of the leaders in architecture and design of several generations of DDR/LPDDR PHYs. She has heavily contributed to design technology co-optimization on Intel internal and external foundry. Priya has been an active member of ESD community at Intel, leading ESD design and verification improvements and innovations. She holds 6 patents, authored/co-authored many publications. She's art loving and enjoys classical music.
Wei-Min Wu
Wei-Min Wu received the dual-Ph.D. degrees in electrical engineering from the KU Leuven, Belgium, and in electronic engineering from National Yang Ming Chiao Tung University (NYCU), Taiwan in 2022. He is now with IMEC, Leuven, Belgium as an RF ESD researcher. His current research interests include ESD protections in Design Technology Co-Optimization (DTCO) with the Si/III-V RF devices and circuits and in high-speed I/O technology.
Authors Corner for 4A.1, 4A.2, and 4A.3
Emerging Technologies Invited Talk: Root Cause Categories for Electrical Over-Stress (EOS) and Electrically Induced Physical Damage (EIPD) on Customer Returns and Qualification Failures
Alfred J. Griffin, Jr.
Al Griffin joined Texas Instruments, Inc. in 1996, and was elected Senior Fellow in February 2020. He has over 30 years of experience in metallurgy, materials science, materials reliability and materials integration, particularly with respect to semiconductor and printed circuit board manufacturing. Al Griffin manages some of TI’s most critical customer return, excursion and qualification issues across all of TI’s technologies and factories and is a founding member of The Red Team, a problem-solving organization. He has worked with most of TI’s top engineers, designers and customers and has collaborated across TI to solve customers’ problems and a wide range of worldwide TI wafer fab and AT issues. Al received his B.S. in Metallurgical Engineering from the University of Texas at El Paso and his Ph.D. and M.S. in Materials Science from Rice University.
Emerging Technologies Invited Talk: Root Cause Categories for Electrical Over-Stress (EOS) and Electrically Induced Physical Damage (EIPD) on Customer Returns and Qualification Failures
Emerging Technologies Talk - Toward a Trillion Transistors - ESD Perspectives on Emerging IC Technologies
Marko Simicic
Marko Simicic received the M.Sc. degree in electrical engineering and information technology from the University of Zagreb, Croatia, in 2012. He obtained a PhD degree from the department of electrical engineering ESAT, KU Leuven, Belgium in 2018. Since 2017 he is an ESD researcher in imec, Belgium. He is a certified ESD control program manager since 2022. He has authored or co-authored more than 40 papers in international journals and conference proceedings. His current research area is rather wide and includes ESD device and circuit design in advanced semiconductor and 3D/2.5D stacking technologies, novel ESD testing and ESD control process assessment.
Emerging Technologies Talk - Toward a Trillion Transistors - ESD Perspectives on Emerging IC Technologies
Emerging Technologies Talk TBA
Emerging Technologies Talk TBA
5A.1 TDDB of Sensitive Gate Dielectrics – Revisited for CDM
Christian C. Russ
Dr. Christian Russ received his MS and PhD degrees in electrical engineering from the Technical University of Munich, Germany, in 1991 and 1999, respectively. He has spent more than 30 years in the field of ESD: from 1994 through 1998, he was with IMEC, Leuven, Belgium, and from 1998 through 2003 he worked for Sarnoff Corporation, Princeton, New Jersey, USA. In 2003, he joined Infineon Technologies, Munich, Germany. In 2011, he transferred to Intel Mobile Communications where he developed ESD concepts for planar and FinFET CMOS technologies. Since 2017, he has been at Infineon Technologies as lead principal engineer for ESD solutions in automotive sensor technologies (Smart Power, CMOS, BiCMOS). Christian was recipient of several Best Paper Awards at the EOS/ESD Symposia (1993, 1996, 1998, 2000, 2001, 2005, 2012 and 2021) and at the ESREF Conference (1993, 1995). He has published over 75 conference and journal publications and has been awarded over 80 patents in his field.
5A.1 TDDB of Sensitive Gate Dielectrics – Revisited for CDM
5A.2 Self-Sufficient ESD Solution for Fail-safe I/O Design in FinFET Technology
Hsin-Yu Chen
Hsin-Yu Chen received the B.S. degree from the Department of Applied Physics, National University of Kaohsiung, Kaohsiung, Taiwan, in 2016, and the M.S. degree from the Institute of Electrophysics, National Chiao-Tung University, Hsinchu, Taiwan, in 2019. She joined Taiwan Semiconductor Manufacturing Company (TSMC) in 2019 and she is in ESD/EOS Technology Department.
5A.2 Self-Sufficient ESD Solution for Fail-safe I/O Design in FinFET Technology
5A.3 Single Event Latch-up (SEL) Rate Prediction Methodology in Bulk FinFET Technology
Tzu-Hao Chiang
Tzu-Hao Chiang received the B.S. degree in electrical engineering and the M.S. degree in electronic engineering from National Taiwan University, Taipei, Taiwan, in 2020. He joined Taiwan Semiconductor Manufacturing Company (TSMC) in 2020, where he is currently a Senior Engineer in ESD/EOS Technology Department. His work is mainly on single event latchup (SEL) and ESD victim design solution development.
5A.3 Single Event Latch-up (SEL) Rate Prediction Methodology in Bulk FinFET Technology
Authors Corner for 5A.1, 5A.2, and 5A.3
Hsin-Yu Chen
Hsin-Yu Chen received the B.S. degree from the Department of Applied Physics, National University of Kaohsiung, Kaohsiung, Taiwan, in 2016, and the M.S. degree from the Institute of Electrophysics, National Chiao-Tung University, Hsinchu, Taiwan, in 2019. She joined Taiwan Semiconductor Manufacturing Company (TSMC) in 2019 and she is in ESD/EOS Technology Department.
Tzu-Hao Chiang
Tzu-Hao Chiang received the B.S. degree in electrical engineering and the M.S. degree in electronic engineering from National Taiwan University, Taipei, Taiwan, in 2020. He joined Taiwan Semiconductor Manufacturing Company (TSMC) in 2020, where he is currently a Senior Engineer in ESD/EOS Technology Department. His work is mainly on single event latchup (SEL) and ESD victim design solution development.
Christian C. Russ
Dr. Christian Russ received his MS and PhD degrees in electrical engineering from the Technical University of Munich, Germany, in 1991 and 1999, respectively. He has spent more than 30 years in the field of ESD: from 1994 through 1998, he was with IMEC, Leuven, Belgium, and from 1998 through 2003 he worked for Sarnoff Corporation, Princeton, New Jersey, USA. In 2003, he joined Infineon Technologies, Munich, Germany. In 2011, he transferred to Intel Mobile Communications where he developed ESD concepts for planar and FinFET CMOS technologies. Since 2017, he has been at Infineon Technologies as lead principal engineer for ESD solutions in automotive sensor technologies (Smart Power, CMOS, BiCMOS). Christian was recipient of several Best Paper Awards at the EOS/ESD Symposia (1993, 1996, 1998, 2000, 2001, 2005, 2012 and 2021) and at the ESREF Conference (1993, 1995). He has published over 75 conference and journal publications and has been awarded over 80 patents in his field.