Wednesday, September 18

9:40 AM

4A.1 Transistor Layout and Technology Impacts on ESD HBM Performance of GaN-on-SiC RF HEMTs

10:05 AM

4A.2 ESD Protection Analysis for 3D NAND Internal Source Plate Discharge Circuit

10:30 AM

4A.3 Efficient Pre-Silicon ESD Verification for Enabling High Performance IO Design

10:55 AM

Authors Corner for 4A.1, 4A.2, and 4A.3

11:15 AM

Emerging Technologies Invited Talk: Root Cause Categories for Electrical Over-Stress (EOS) and Electrically Induced Physical Damage (EIPD) on Customer Returns and Qualification Failures

2:55 PM

Emerging Technologies Talk - Toward a Trillion Transistors - ESD Perspectives on Emerging IC Technologies

3:45 PM

Emerging Technologies Talk TBA

4:55 PM

5A.1 TDDB of Sensitive Gate Dielectrics – Revisited for CDM

5:20 PM

5A.2 Self-Sufficient ESD Solution for Fail-safe I/O Design in FinFET Technology

5:45 PM

5A.3 Single Event Latch-up (SEL) Rate Prediction Methodology in Bulk FinFET Technology

6:10 PM

Authors Corner for 5A.1, 5A.2, and 5A.3