Agenda

Elyse Rosenbaum is the Melvin and Anne Louise Hassebrock Professor in Electrical and Computer Engineering at the University of Illinois at Urbana-Champaign. She received the Ph.D. degree in electrical engineering from the University of California, Berkeley. She is the director of the NSF-supported Center for Advanced Electronics through Machine Learning (CAEML), a joint project of the University of Illinois, Georgia Tech and North Carolina State University. Her current research interests include machine-learning aided behavioral modeling of microelectronic components and systems, compact models, ESD-robust high-speed I/O circuit design, CDM device characterization, and generative modeling of lifetime distributions. Dr. Rosenbaum has authored or co-authored over 200 technical papers; she has been an editor for IEEE Transactions on Device and Materials Reliability and IEEE Transactions on Electron Devices. She was the recipient of a Best Student Paper Award from the IEDM, Outstanding Paper Award and 2 Best Paper Awards from the EOS/ESD Symposium, a Technical Excellence Award from the SRC, an NSF CAREER award, an IBM Faculty Award, and the ESD Association's Industry Pioneer Recognition Award. She is a Fellow of the IEEE.

Heinrich Wolf received his PhD from the Technical University of Berlin, Germany. In 1999, he joined the Munich branch of the Fraunhofer Institute for Reliability and Microintegration (IZM), which became the Fraunhofer Institute for Electronic Microsystems and Solid State Technologies EMFT. In his role as an expert in test and measurement, he became chief scientist at the EMFT and co-leads the Test of Electronic and Quantum Systems (TEQ) group. He also co-chairs the CDM Joint Working Group in the standardization body of the ESD Association, and represents the German ESD-Forum in the standards working groups.

Kathleen Muhonen is currently a Principal Development Engineer at Qorvo in Greensboro, NC. She is involved in developing ESD on-chip protection and ESD instrumentation for better characterization of clamps. Previous work included RF characterization and model support for power amplifiers and switches. This included developing state-of-the-art harmonic characterization and improved de-embedding techniques of SOI switches. Previous experience includes assistant professor at Penn State Erie, Hewlett Packard and Lockheed Martin. Kathleen is a member of the ESDA and of all device testing standards committees. Kathleen has BSEE from Michigan Technological University, MSEE from Syracuse University and Ph.D.EE from Penn State University.

Benjamin J. Orr was born in Seattle, Washington, in 1989. He received a B.S. in both electrical and computer engineering in 2011 and a Ph.D. in electrical engineering in 2016 from the Missouri University of Science and Technology. During his doctoral work which he completed three co-ops at Intel Mobile Communications in Munich Germany modeling ESD-induced soft failures.
Upon graduation, Benjamin returned home to the pacific northwest, joining the Intel Corporation in Hillsboro, OR as a process reliability ESD engineer. His research interests include optimization of ESD protection devices, novel ESD protection devices, and statistical characterization of process ESD performance.

Priya has a master’s degree in EE with 27 years of Industry experience. Her areas of expertise include high speed IO design, Memory Sub-system architecture, integration and verification chiplet-based 3D ICs, Process technology Co-optimization (DTCO). Currently, she is a Principal Engineer at Intel, leading Memory IO Design and PHY integration, driving power, area and performance optimization and providing technical leadership for innovations in state-of-the-art IO design and methodologies. Recently, she has been involved in LPDDR6/DDR6 Nextgen circuit memory IO architecture and platform definition. Priya is a recognized Device and Interconnect Reliability expert at Intel. Owned innovations and enhancements for reliability and device technology definition. Well Sought after ESD expert, pioneered Industry’s first cross-die ESD verification flow for 3D Hetero stack. She holds 6 patents, authored/co-authored many publications.