Monday, September 28
1A.1 Impact of Process and Fab-to-Fab Variations to ESD Robustness of Snapback-Based ESD Protection Devices
Gianluca Boselli
Gianluca Boselli earned his MS in EE from the University of Parma (1996) and PhD from the University of Twente (2001). He joined Texas Instruments in 2001, focusing on ESD and latch-up for CMOS technologies. He currently manages TI's corporate ESD Team and directs the Advanced Technology Development University Research Program. A prolific author and speaker, he has received multiple best paper awards and the prestigious ESD Association Outstanding Contribution Award (2019). He holds 20+ patents, serves on the EOS/ESD Association Board of Directors as Chief Strategist, and is an IEEE Senior Member.
1A.2 Mechanism of Premature ESD Failure Adjacent HV PNP ESD Device under IO-to-IO Stress
Jehoon Lee
Jehoon Lee received his B.S., M.S., and Ph.D. degrees in Electronic and Electrical Engineering from Dankook University (DKU), Korea, in 2016, 2018, and 2023, respectively. He is currently with the ESD/TCAD Team at DBHiTek. His research focuses on ESD protection design in BCD, CIS, LDI, and other processes, as well as TCAD-based device analysis.
Authors Corner for 1A.1 & 1A.2
Gianluca Boselli
Gianluca Boselli earned his MS in EE from the University of Parma (1996) and PhD from the University of Twente (2001). He joined Texas Instruments in 2001, focusing on ESD and latch-up for CMOS technologies. He currently manages TI's corporate ESD Team and directs the Advanced Technology Development University Research Program. A prolific author and speaker, he has received multiple best paper awards and the prestigious ESD Association Outstanding Contribution Award (2019). He holds 20+ patents, serves on the EOS/ESD Association Board of Directors as Chief Strategist, and is an IEEE Senior Member.
Jehoon Lee
Jehoon Lee received his B.S., M.S., and Ph.D. degrees in Electronic and Electrical Engineering from Dankook University (DKU), Korea, in 2016, 2018, and 2023, respectively. He is currently with the ESD/TCAD Team at DBHiTek. His research focuses on ESD protection design in BCD, CIS, LDI, and other processes, as well as TCAD-based device analysis.
System-Level Characterization Issues Interactive Seminar
Hans Kunz
Hans Kunz joined Texas Instruments in 2003, after nine years at Dallas Semiconductor/Maxim, and was elected Distinguished Member of Technical Staff in 2017. His past responsibilities include designing, developing, and implementing ESD protection circuits for analog CMOS and high-voltage BiCMOS technologies, as well as developing ESD verification tools and methodologies. Hans is currently focused on developing test, measurement, and design methodologies for system-level ESD protection at the IC level. Hans is a co-author of multiple publications on ESD and received the Best Presentation Award at the 2006 EOS/ESD Symposium. He holds 13 patents.
2A.1 Characterization and Benchmarking of ESD Diodes in CFET Technology
Wen-Chieh Chen
Wen-Chieh Chen received the B.S and M.S. degrees in electronics engineering from National Chiao-Tung University, Hsinchu, Taiwan, in 2016 and 2018, respectively, and the Ph.D. degree from the Electrical Engineering Department (ESAT), Katholieke Universiteit Leuven (KU Leuven), Leuven, Belgium, in 2024. She joined the ESD team, imec, Leuven, Belgium, in 2019. Her current research interests include mixed-voltage I/O design and ESD characterization in advanced sub-5-nm technologies, 3D/2.5D ICs, and the DTCO/STCO scaling roadmap.
2A.2 Nanosheet Sub-ns ESD Endurance and I/O Circuit Co-Optimization for ESD Risk Mitigation
Tzu-Hao Chiang
Tzu-Hao Chiang received the B.S. degree in electrical engineering and the M.S. degree in electronic engineering from National Taiwan University, Taipei, Taiwan, in 2020. He joined Taiwan Semiconductor Manufacturing Company (TSMC) in 2020, where he is currently a senior engineer in the ESD/EOS Technology Department. His work focuses on single-event latch-up (SEL) and ESD victim design solution development.
2A.3 Impact of Buried Power Rails on Thin-Substrate ESD Diode Performance
Emanuele Groppo
Emanuele Groppo received his B.Sc. (2020) and M.Sc. (2022) in Electronic Engineering from Politecnico di Torino, Italy. He is currently pursuing a Ph.D. at the Technical University of Munich (TUM), Chair of Circuit Design. In 2023, he joined the ESD team at Intel in Munich, Germany. The focus of his research is on novel ESD devices and solutions for advanced semiconductor technologies.
Authors Corner for 2A.1, 2A.2, and 2A.3
Wen-Chieh Chen
Wen-Chieh Chen received the B.S and M.S. degrees in electronics engineering from National Chiao-Tung University, Hsinchu, Taiwan, in 2016 and 2018, respectively, and the Ph.D. degree from the Electrical Engineering Department (ESAT), Katholieke Universiteit Leuven (KU Leuven), Leuven, Belgium, in 2024. She joined the ESD team, imec, Leuven, Belgium, in 2019. Her current research interests include mixed-voltage I/O design and ESD characterization in advanced sub-5-nm technologies, 3D/2.5D ICs, and the DTCO/STCO scaling roadmap.
Tzu-Hao Chiang
Tzu-Hao Chiang received the B.S. degree in electrical engineering and the M.S. degree in electronic engineering from National Taiwan University, Taipei, Taiwan, in 2020. He joined Taiwan Semiconductor Manufacturing Company (TSMC) in 2020, where he is currently a senior engineer in the ESD/EOS Technology Department. His work focuses on single-event latch-up (SEL) and ESD victim design solution development.
Emanuele Groppo
Emanuele Groppo received his B.Sc. (2020) and M.Sc. (2022) in Electronic Engineering from Politecnico di Torino, Italy. He is currently pursuing a Ph.D. at the Technical University of Munich (TUM), Chair of Circuit Design. In 2023, he joined the ESD team at Intel in Munich, Germany. The focus of his research is on novel ESD devices and solutions for advanced semiconductor technologies.