Monday, September 28
1A.1 Impact of Process and Fab-to-Fab Variations to ESD Robustness of Snapback-Based ESD Protection Devices
Gianluca Boselli
Gianluca Boselli earned his MS in EE from the University of Parma (1996) and PhD from the University of Twente (2001). He joined Texas Instruments in 2001, focusing on ESD and latch-up for CMOS technologies. He currently manages TI's corporate ESD Team and directs the Advanced Technology Development University Research Program. A prolific author and speaker, he has received multiple best paper awards and the prestigious ESD Association Outstanding Contribution Award (2019). He holds 20+ patents, serves on the EOS/ESD Association Board of Directors as Chief Strategist, and is an IEEE Senior Member.
1A.2 Mechanism of Premature ESD Failure Adjacent HV PNP ESD Device under IO-to-IO Stress
Jehoon Lee
Jehoon Lee received his B.S., M.S., and Ph.D. degrees in Electronic and Electrical Engineering from Dankook University (DKU), Korea, in 2016, 2018, and 2023, respectively. He is currently with the ESD/TCAD Team at DBHiTek. His research focuses on ESD protection design in BCD, CIS, LDI, and other processes, as well as TCAD-based device analysis.
Interactive Seminar: Applying Air-discharge ESD to conductors: Is it time to stop the madness?
Hans Kunz
Hans Kunz joined Texas Instruments in 2003, after nine years at Dallas Semiconductor/Maxim, and was elected Distinguished Member of Technical Staff in 2017. His past responsibilities include designing, developing, and implementing ESD protection circuits for analog CMOS and high-voltage BiCMOS technologies, as well as developing ESD verification tools and methodologies. Hans is currently focused on developing test, measurement, and design methodologies for system-level ESD protection at the IC level. Hans is a co-author of multiple publications on ESD and received the Best Presentation Award at the 2006 EOS/ESD Symposium. He holds 13 patents.
2A.1 Characterization and Benchmarking of ESD Diodes in CFET Technology
Wen-Chieh Chen
Wen-Chieh Chen received the B.S and M.S. degrees in electronics engineering from National Chiao-Tung University, Hsinchu, Taiwan, in 2016 and 2018, respectively, and the Ph.D. degree from the Electrical Engineering Department (ESAT), Katholieke Universiteit Leuven (KU Leuven), Leuven, Belgium, in 2024. She joined the ESD team, imec, Leuven, Belgium, in 2019. Her current research interests include mixed-voltage I/O design and ESD characterization in advanced sub-5-nm technologies, 3D/2.5D ICs, and the DTCO/STCO scaling roadmap.
2A.2 Nanosheet Sub-ns ESD Endurance and I/O Circuit Co-Optimization for ESD Risk Mitigation
Tzu-Hao Chiang
Tzu-Hao Chiang received the B.S. degree in electrical engineering and the M.S. degree in electronic engineering from National Taiwan University, Taipei, Taiwan, in 2020. He joined Taiwan Semiconductor Manufacturing Company (TSMC) in 2020, where he is currently a senior engineer in the ESD/EOS Technology Department. His work focuses on single-event latch-up (SEL) and ESD victim design solution development.
2A.3 Impact of Buried Power Rails on Thin-Substrate ESD Diode Performance
Emanuele Groppo
Emanuele Groppo received his B.Sc. (2020) and M.Sc. (2022) in Electronic Engineering from Politecnico di Torino, Italy. He is currently pursuing a Ph.D. at the Technical University of Munich (TUM), Chair of Circuit Design. In 2023, he joined the ESD team at Intel in Munich, Germany. The focus of his research is on novel ESD devices and solutions for advanced semiconductor technologies.
Tuesday, September 29
3A.1 Detection-Based System-Level ESD Management Using Inactive CMOS Pins in High-Speed DDR Interfaces
Jun-Bae Kim
Jun‑Bae Kim holds a Ph.D. in electrical engineering and is a Principal Engineer at Samsung Electronics with over 20 years of experience in DRAM circuit design and reliability. He spent more than a decade on DRAM I/O, high‑speed interface, and signal‑integrity design, then transitioned to system‑level ESD engineering, investigating ESD‑induced failures in high‑speed memory and EMI mitigation for mobile DRAM. Since 2024, he has tackled ESD challenges in stacked‑DRAM packaging and manufacturing. His current research focuses on system‑level ESD, the charged‑device model (CDM), and ESD‑aware design methodologies.
3A.2 A Physics-Informed Deep Learning Model for Standardized Air Discharge ESD Waveform Monitoring
Ruoyu Hu
Ruoyu Hu is currently working as a reliability engineer at Amazon. Ruoyu received his PhD from the University of Southampton, with a major in Bioelectronic Sensors. Before that, he earned his Master of Engineering degree in electronics from the University of Edinburgh. He was awarded a Bachelor's degree in Electronic Engineering and Automation from Beijing Institute of Technology. Ruoyu worked at Neuron Network on CV-related research and on their automation application at Amazon. He also dives deep into ESD-related research and protection methodology related to tests.
3A.3 Pre-Spark Charge Loss During Air-Discharge ESD Testing
Hans Kunz
Hans Kunz joined Texas Instruments in 2003, after nine years at Dallas Semiconductor/Maxim, and was elected Distinguished Member of Technical Staff in 2017. His past responsibilities include designing, developing, and implementing ESD protection circuits for analog CMOS and high-voltage BiCMOS technologies, as well as developing ESD verification tools and methodologies. Hans is currently focused on developing test, measurement, and design methodologies for system-level ESD protection at the IC level. Hans is a co-author of multiple publications on ESD and received the Best Presentation Award at the 2006 EOS/ESD Symposium. He holds 13 patents.
4A.1 Overview of Standalone MOS Based Protections and Network Integrations
Johan Bourgeat
Johan received his PhD in 2011, specializing in innovative ESD (Electrostatic Discharge) devices in the C28SOI node. He joined STMicroelectronics, where he has dedicated his expertise to developing new SCR-based ESD solutions. Over the years, Johan has been responsible for advancing ESD protections for analog, RF, and high-voltage applications, as well as addressing latch-up issues in CMOS, Bi-CMOS, and PIC technologies.
He is currently an active member of the technical staff community and serves on the ESD/EOS/EMC/Latch-Up Steering Committee. Recently, he has taken on the leadership role of the TDP/IPLD ESD Team based in Crolles. Johan is also an innovative contributor to the field, regularly filing patents and publishing at various scientific conferences.
4A.2 HV Power Stage Protection with NLDMOS-SCR
Vladislav Vashchenko
Dr. Vladislav Vashchenko has been the Sr. Director, Power ESD Group at Analog Devices Corp since 2011. He is responsible for aspects of power analog ESD/Latch-up IC co-design business process and technology development. Previously, he managed ESD technology development at National Semiconductor (2000-2011). He received an MS Engineer-Physicist (1987), a Ph.D. in Physics of Semiconductors from MIPT (1990), and a "Doctor of Science in Microelectronics" habilitation degree (1997). He is the author of 150 U.S. patents, over 120 papers, and co-author of three books in the ESD field.
5A.1 Evaluation of a Short Event between the Supply Voltage and a SuperSpeed Line in a USB-C Connector for the Standard and Extended Power Range
Steffen Holland
Steffen Holland received his PhD in Physics from the University of Hamburg. He joined Nexperia's bipolar process development group in Hamburg, Germany, in 2005. The focus of his work quickly became TCAD process and device simulations for discrete ESD protection devices. He now works on TVS protection devices. His interests are system-level ESD simulations, and he is chair of the ESDA working group 26. He serves on the Board of Directors at the ESDA.
5A.2 ESD Robustness of AC-Coupling Capacitors in Differential High-Speed Interfaces
Martin Pilaski
Martin holds a diploma* in Computer Engineering from Mannheim University. He joined Philips Semiconductors in 2005 and has since then worked in several product design and application marketing roles for NXP and Nexperia. Martin is currently responsible for worldwide product application support of Nexperia's ESD Protection and Filtering portfolio with a focus on mobile, portable, consumer, and computing applications.
5A.3 Scalable ESD Modeling of Non-Linear Multilayer Ceramic Capacitor Under System-Level ESD
Kendrik Emkel Ginting
Kendrik Emkel Ginting received the B.Sc. degree in Electrical Engineering from Bandung Institute of Technology (ITB), Indonesia, in 2023, and the M.Sc. degree in Communications and Electronics Engineering from the Technical University of Munich (TUM), Germany, in 2025.
From 2024 to 2026, he was with the ESD Department of Infineon Technologies AG, Neubiberg, Germany, where he worked on system-level electrostatic discharge (ESD). Since February 2026, he has been a University Project Assistant at Graz University of Technology, Austria, where he conducts research on ESD and electromagnetic compatibility (EMC). His research interests include system-level ESD, EMC, and reliability.
Wednesday, September 30
6A.1 Low Leakage Protection for 1.2V Analog Circuit Blocks in Power Technologies
Vladislav Vashchenko
Dr. Vladislav Vashchenko has been the Sr. Director, Power ESD Group at Analog Devices Corp since 2011. He is responsible for aspects of power analog ESD/Latch-up IC co-design business process and technology development. Previously, he managed ESD technology development at National Semiconductor (2000-2011). He received an MS Engineer-Physicist (1987), a Ph.D. in Physics of Semiconductors from MIPT (1990), and a "Doctor of Science in Microelectronics" habilitation degree (1997). He is the author of 150 U.S. patents, over 120 papers, and co-author of three books in the ESD field.
6A.2 On-Chip Gate ESD Protection for 650V E-Mode GaN HEMT Using 2DEG Resistor Between Trigger and Discharge Element
Nandha Kumar Subramani
Nandha Kumar Subramani received his PhD in Electronics Engineering from the Université de Limoges, France, in 2017, and his master's degree in Electrical and Electronics Engineering from the University of Sheffield in 2014. He has worked for GLOBALFOUNDRIES on ESD devices development and characterization, and TCAD device modeling. He has authored or co-authored several publications in the fields of GaN trap characterization, low-frequency noise measurements, TCAD-based physical simulations, and ESD device development.
6A.3 Investigation of High Voltage Grounded Ntype Well Latch-up Robustness in 55nm BCDLite Technology
Alwyn Rebello
Alwyn Rebello received an M.Sc. degree in Physics from Cochin University of Science and Technology, Kerala, India, in 2005, and a Ph.D. degree from the National University of Singapore (NUS), Singapore, in 2011. In 2017, he joined GLOBALFOUNDRIES in Singapore, where he is involved in the development of ESD and Latchup protection for technology nodes ranging from 0.18 μm to 28nm. His current research interests include ESD device development and latch-up prevention for various automotive and RF applications.