Sunday, September 27
EOS/ESD Association, Inc. Annual Meeting & Reception - Open to All Attendees
Monday, September 28
Opening Welcome
James Di Sarro
Dr. James Di Sarro received the B.S. degree (summa cum laude) in electrical engineering and economics from Duke University, Durham, NC, in 2004, and the M.S. and Ph.D. degrees in electrical and computer engineering from the University of Illinois Urbana-Champaign, Urbana, IL, in 2006 and 2009, respectively. He is currently a Member of the Group Technical Staff at Texas Instruments in Dallas, TX, working on product-level ESD protection circuit design and verification. From 2009 to 2013, he worked on ESD devices and compact model development for advanced CMOS technologies as an Advisory Engineer/Scientist at IBM Corporation. While a student, he completed several summer internships at IBM Corporation and National Semiconductor in electrostatic discharge (ESD) protection device development. He has 29 granted patents and has authored or co-authored 15 conference presentations and journal papers. Dr. Di Sarro received an IBM Ph.D. Fellowship and an EOS/ESD Symposium Best Student
Paper Award.
Keynote: Deep Neural Networks and Transfer Learning: Unlocking the Potential for ESD Data Analysis and Simulations
Mehrdad Nourani
Mehrdad Nourani received a Ph.D. in computer engineering from Case Western Reserve University, Cleveland, Ohio. He joined the University of Texas at Dallas in 1999, where he is currently a Professor of Electrical & Computer Engineering and Associate Provost. Dr. Nourani's research interests include system-on-chip design & test, design for reliability, signal/image processing, machine learning for risk assessment and prediction for mission-critical devices and systems. His research has been supported by the National Science Foundation, Semiconductor Research Corporation, and industry. Dr. Nourani holds seven utility patents and has published more than 300 papers in peer-reviewed journals and conference proceedings.
Networking Break
2027 ESDA Roadmap Update
Symposium Paper Awards Presentation Lunch
James Di Sarro
Dr. James Di Sarro received the B.S. degree (summa cum laude) in electrical engineering and economics from Duke University, Durham, NC, in 2004, and the M.S. and Ph.D. degrees in electrical and computer engineering from the University of Illinois Urbana-Champaign, Urbana, IL, in 2006 and 2009, respectively. He is currently a Member of the Group Technical Staff at Texas Instruments in Dallas, TX, working on product-level ESD protection circuit design and verification. From 2009 to 2013, he worked on ESD devices and compact model development for advanced CMOS technologies as an Advisory Engineer/Scientist at IBM Corporation. While a student, he completed several summer internships at IBM Corporation and National Semiconductor in electrostatic discharge (ESD) protection device development. He has 29 granted patents and has authored or co-authored 15 conference presentations and journal papers. Dr. Di Sarro received an IBM Ph.D. Fellowship and an EOS/ESD Symposium Best Student
Paper Award.
Alain Louiseau
Alain Loiseau received a maîtrise in Electrical Engineering from the Université des Sciences et Techniques du Languedoc, France, in 1993 and a master's in electrical engineering from the University of Virginia in 1995. He has worked for IBM, STMicro, and GLOBALFOUNDRIES on CMOS technology development and characterization, CPU power reduction, flash array functional testing, high-voltage FET reliability, and ESD. He holds over 100 US patents and has (co)-authored 13 papers.
Year in Review: ESD Protection Challenges and Strategies in Advanced CMOS Technologies
Wen-Chieh Chen
Wen-Chieh Chen received the B.S and M.S. degrees in electronics engineering from National Chiao-Tung University, Hsinchu, Taiwan, in 2016 and 2018, respectively, and the Ph.D. degree from the Electrical Engineering Department (ESAT), Katholieke Universiteit Leuven (KU Leuven), Leuven, Belgium, in 2024. She joined the ESD team, imec, Leuven, Belgium, in 2019. Her current research interests include mixed-voltage I/O design and ESD characterization in advanced sub-5-nm technologies, 3D/2.5D ICs, and the DTCO/STCO scaling roadmap.