Agenda

Due to the ongoing trend of more electronic components in the car there is the need for more and faster data transfer.

• The older standards CAN and LIN give way to faster protocols such as the Open Alliance Ethernet standard which allows data rates of up to 1Gbit/s. It is clear that the journey doesn’t end here and even higher data rates will be required in the future.
• The more sophisticated electronics applications also require more computing power which can only be realized with ICS manufactured in advanced CMOS processes.

Both trends raise the requirements for the whole system: parasitic capacitances need to be reduced to maintain signal integrity and at the same time ICs in advanced process nodes are more vulnerable to ESD. Providing an adequate ESD protection on IC level might become costly and/or reduce signal integrity. Therefore, system level ESD protection becomes more challenging as older concepts may no longer work and in addition other requirements need to be met.

In the workshop the following topics will be discussed:

• Presentation of current architecture (Open Alliance)
• What are your current needs for a good system level automotive design?
• What is your approach for providing (system level) ESD protection?
• Do you have the tools and information you need to achieve your aim?
• How could it look in the future? What is then needed in terms of tools and information?
• Is there a need for a change of the way of working?
• Will a co-design along the vertical value chain (component supplier/Tier1/OEM) be required or is it already needed today?

The purpose of this discussion group is to go through the differences between ANSI/ESD S20.20 requirements and recommendations for best practices for ESD/ESA control in semiconductor wafer fab and mask house facilities.

Several semiconductor integrated device manufacturing (IDM) representatives have stated that their customers have requested that the IDMs provide proof and/or certification that their established ESD/ESA control program is sufficient for their respective semiconductor manufacturing processes.

ANSI/ESD S20.20 has been in place for over 24 years as a means to establish a certifiable ESD control program for electronics manufacturing facilities that handle and process ESD sensitive electronic components. Typically, ANSI/ESD S20.20 has not been used to certify semiconductor wafer fab and mask house facilities. However, there are other documents published by SEMI that address best practices for such facilities (SEMI E78: Guide to Assess and Control Electrostatic Discharge (ESD) and Electrostatic Attraction (ESA) for Equipment; SEMI E129: Guide to Assess and Control Electrostatic Charge in a Semiconductor Manufacturing Facility, and SEMI E163: Guide for the Handling of Reticles and Other Extremely Electrostatic Sensitive (EES) Items Within Specially Designated Areas).

While semiconductor fabs have some level of ESD/ESA controls in place, they don’t typically establish an ESD control program certifying to ANSI/ESD S20.20. ESD/ESA control methodologies in a fab are covered in different areas of responsibility (quality, manufacturing, process control, tool maintenance, etc.), so it can be challenging to pull together a consensus that would prove that the facility has proper controls in place for all ESD/ESA risks.

Currently, there is a group of volunteers working on creating a document that will review semiconductor manufacturing ESD/ESA challenges, considerations, and best practices and compare and contrast semiconductor wafer and mask house manufacturing ESD/ESA best practices to for electronics manufacturing and assembly which ANSI/ESD S20.20 is designed for. The hope is to have this document published before the Symposium to aid in the discussion.

ESD designers are facing new challenges due to sub-nanosecond voltage stress. Such short pulses may result from the turn-on delay of ESD clamps or the overshoot of ESD diodes, for example. Increased layout parasitics (R, C, L) may further exacerbate this effect. Ultra-short stress may also happen during ESD discharge of die-to-die interface pins during a 3D bonding process of chiplets where pulse widths as short as a few tens of picoseconds are being predicted. The MOSFETs inside IO circuits may still suffer damage due to gate oxide stress and Drain-Source snapback.

In mature technologies (planar CMOS), MOSFETs have typically been able to survive snapback with 1ns TLP pulses. However, in advanced technology nodes (FinFET and beyond), MOSFETs may immediately fail after snapback. Methods to increase the BJT failure current It2, like silicide-blocking, may not be available anymore.

In this workshop, we will discuss pulse length limitations of TLP testing, possible new methods for characterizing devices in the sub-nanosecond regime, the need for accurate ESD device simulation models, and how to optimize ESD designs without wasting die area under this new challenge.