Saturday, September 14

8:30 AM
8:30 AM - 4:30 PM PDT

Introduction to On-Chip ESD Protection

The tutorial is designed to provide a comprehensive understanding of electrostatic discharge (ESD) events and its implications on semiconductor devices. The tutorial will delve into the fundamentals of ESD, including the physics behind the electrostatic build-up and discharge processes. Integrated circuits can get damaged by ESD events during manufacturing, testing or in assembly when they are handled by people or machines. IC layout engineers can influence the robustness of their circuits by applying guidelines and tricks. Participants will explore various ESD protection strategies and design methodologies used in modern integrated circuits (ICs). The material will cover ESD devices used from basic CMOS to advanced FinFET technologies. The session will cover key topics such as on-chip ESD protection device structures and layout considerations, Through a blend of theoretical knowledge and practical examples, the tutorial aims to equip attendees with the skills necessary to understand on-chip ESD protection schemes. This tutorial is ideal for IC engineers seeking to enhance their expertise in ESD protection for semiconductor devices.   

Oliver Marichal

Oliver Marichal

Chief Engineer
SOFICS

Olivier Marichal graduated from Katholieke Universiteit Leuven with a degree in Electrical Engineering in 2003 and has since dedicated his career to the field of Electrostatic Discharge (ESD) protection design, currently serving as Chief Engineering at Sofics. His journey with the company began shortly after graduation as an ESD engineer, and over the years, Olivier has worked on many projects, covering a broad range of technologies from High Voltage BCD to the latest nanometer Finfet processes. His professional focus is on continuously adding value to customers through his work, delivering state-of-the-art ESD solutions for the ever-evolving landscape of semiconductor applications.

Olivier has (co-)authored several papers on ESD and contributed as an inventor on many patents. In addition to his technical contributions, Olivier is dedicated to sharing his knowledge and insights. He has conducted several tutorials on on-chip ESD protection design for industry professionals around the world.

Introduction to On-Chip ESD Protection

Sunday, September 15

8:30 AM
8:30 AM - 12:00 PM PDT

Introduction to Characterization of On-Chip ESD Protection

Abstract

This course is about characterizing the Electrostatic Discharge (ESD) robustness of semiconductor circuits and protection solutions. It includes the typical measurement techniques like HBM, MM, CDM, TLP, VF-TLP, HMM, and IEC 61000-4-2 used in the industry. The material provides an overview of the advantages and disadvantages of each technique.
 
The tutorial will also cover the interpretation of test results. Emphasis will be placed on understanding the trade-offs and design considerations in optimizing ESD protection devices for different applications.
 
This tutorial is tailored for professionals in semiconductor device design and testing, seeking to deepen their expertise in ESD characterization. 

Learning Outcomes

  • Understanding ESD Characterization Techniques: Learn about the various techniques and methodologies used in the characterization of ESD protection devices.
  • Familiarity with ESD Test Models: Learn about different ESD test models, such as Human Body Model (HBM), Machine Model (MM), and Charged Device Model (CDM), and their applications in device testing.
  • Understand usage of Test Equipment: Understand the usage of specialized equipment for ESD characterisation, such as Transmission Line Pulse (TLP) testing systems.
  • Interpreting Test Data: Develop the ability to analyze and interpret test results to assess the performance and reliability of ESD protection structures.
Wim Vanhouteghem

Wim Vanhouteghem

Senior ESD Design Engineer and Head of Measurement Lab
Sofics

Wim Vanhouteghem is a Senior ESD Design Engineer and the head of the measurement lab at Sofics. A 2007 graduate of KHBO (now part of the Catholic University of Leuven), Wim joined Sofics immediately after completing his studies. His work primarily focuses on ESD protection in semiconductor technologies, ranging from high-voltage BCD to FinFETs.


Wim has plenty of experience in implementing ESD protection and conducting ESD measurements. He contributed to the SEED concept and has worked on system-level ESD measurements on bare dies. 

Introduction to Characterization of On-Chip ESD Protection

1:00 PM
1:00 PM - 2:30 PM PDT

Overview on ESD and Latch-up Challenges in 2.5D and 3D-Stacked ICs

2.5D and 3D integration are commercially available packaging options in the semiconductor industry. The Industry Council on ESD targets level is working on a white paper that discusses the ESD challenges of die-to-die interfaces in 2.5D/3D stacked ICs. In this invited talk, we provide an overview of the ESD and latch-up challenges that are currently solved or need to be solved in the near future. We discuss the impact of 3D integration on the ESD and latch-up robustness. ESD testing challenges like the assessment of the CDM robustness of internal IOs are covered and the specific requirements for the ESD protection design in 2.5D/3D stacked ICs are discussed. Our talk will show that all ingredients for the successful enablement of commercial 2.5D/3D stacked ICs are ready to be used.

 

 

Mirko Scholz

Mirko Scholz

Principal Engineer in ESD Development
Infineon Technologies AG

Dr. Mirko Scholz received his Ph.D. in Electrical Engineering from the Vrije Universiteit in Brussels (VUB) in 2013. From 2005 until 2017, he was working as an ESD researcher at imec in Leuven/Belgium. From March 2017 until June 2019, he was a program manager at the imec academy and in imec’s process technology transfer activities. Since July 2019, he has been with Infineon Technologies in Munich/Germany, where he is a Principal Engineer in ESD Development. His daily work focuses on component- and system-level ESD protection design for several RF and sensor product lines at Infineon.

Since 2007 he has been an active member of different working groups in the ESDA standards committee, currently co-chairing WG 5.6 (Human Metal Model). He was the management chair of the IEW 2018 in Belgium. Since 2019 he has been a member of the steering committee of the EOS/ESD Symposium. In this function, he is the Technical Program Committee (TPC) chair of the EOS/ESD Symposium 2023. For the 2017-2019 term and again for the 2022-2024 term, he has been an elected member of the ESDA Board of Directors. Since 2017, he has been heading the business unit of the Advanced Topics Committee of the ESDA.

He has authored/co-authored more than 100 publications, tutorials, and patents in the field of ESD design and testing. He is co-author of the 2014 Springer book “System-level ESD Protection”. He is a regular reviewer for several IEEE journals and a current member of the IRPS sub-committee on ESD and Latchup.

Overview on ESD and Latch-up Challenges in 2.5D and 3D-Stacked ICs

3:00 PM
3:00 PM - 4:30 PM PDT

ESD Design Challenges of RF and High Speed I/Os

RF and high speed I/Os are typically very challenging to protect against ESD stresses. This is due to the very limited ESD protection capacitance load “budget” of those pins for functional reasons. Furthermore, as the advanced CMOS technology has evolved towards 5 nm FinFET and beyond, the thinner gate oxide makes the devices become more vulnerable to ESD zaps. At the same time, a trend of a 2X increase of per-pin data rate every 4 years is observed for high-speed SerDes wireline I/Os (e.g., USB, Ethernet, etc.), and higher bandwidth is required for RF I/Os of Millimeter wave Transceivers.
This presentation will cover the following topics:
•    The increase of data rate and bandwidth requirement for every SerDes generation and the advanced CMOS technology gate oxide scaling related aspects
•    The ESD design trade-offs and challenges of RF and High-Speed I/O’s
•    The examples of ESD design techniques applicable to RF and high-speed I/O’s (RF ESD co-design, T-coil design, etc.)
•    The lowering of CDM level for ultra-high-speed I/O interfaces (recommendation by the Industry Council on ESD Target Levels)

Dolphin Abessolo-Bidzo

Dolphin Abessolo-Bidzo

Senior Principal RF ESD & Latch-Up Design Engineer
NXP Semiconductors

Dr. Ir. Dolphin Abessolo-Bidzo received his M.Sc. (2004) and his Ph.D. (2007) in Electrical Engineering from ENSICAEN and from the University of Basse-Normandie, France. He is currently working as Senior Principal RF ESD & Latch-Up Design Engineer for advanced RFCMOS and BiCMOS technologies of RF and Millimeter wave applications at NXP Semiconductors.

Dolphin has published numerous articles and papers in IEEE scientific journals, symposia, and conferences on ESD, RF, and time domain analysis and holds several patents in the field of ESD protection of integrated circuits (ICs).

He is an active member of the ESDA Workgroup-18 on Electronic Design Automation (EDA) for ESD. For more than 15 years, he has regularly served in the management and the technical program committees of the International Electrostatic Discharge Workshops (IEW’s) and the EOS/ESD Symposia. Dolphin was the Management Committee General Chair of the IEW2023 in Germany and is a 2024 member of the Board of Directors.

ESD Design Challenges of RF and High Speed I/Os