Monday, September 15

8:00 AM

Opening Welcome

8:30 AM

Keynote: Small Wonders, Monumental Impact: The World of Semiconductor Innovation

9:40 AM
10:50 AM

1A.1 ESD Considerations for Photonics Products

11:15 AM

1A.2 ESD HBM Failures of Different Cap Layer and Barrier Thinning Effects in GaN-on-Si AlGaN/GaN HEMTs

11:40 AM

Authors Corner 1A.1 & 1A.2

1:00 PM

Presentation and Interactive Workshop - System Level Direct Pin ESD – The White Elephant in the Room for System ESD Testing

3:10 PM

Invited Talk - Statistical Characterization of Human-Induced ESD for Field Risk Assessment

4:20 PM

2A.1 Transient Response of Very Fast Transmission Line Pulse: Procedures for Measurement Verification

4:45 PM

2A.2 Statistical Analysis of (VF-)TLP Parameter Variability

5:10 PM

2A.3 AI-Driven Analysis of VF-TLP and TLP Characteristics via Hierarchical Clustering

5:35 PM

2A.1, 2A.2, & 2A.3 Authors Corner

Tuesday, September 16

8:00 AM

Morning Welcome

8:10 AM

GaN Devices: Technology, Reliability-Limiting Processes and ESD Failures

9:45 AM

3A.1 Innovative ESD Protection for RF Circuits: Integrating Diodes into Capacitors in Advanced Technology

10:10 AM

3A.2 Low-C ESD Protection Design With Improved BEOL Layout Style for High-Frequency Applications

10:35 AM

3A.3 CDM Protection of an Antenna Pad in CMOS Technology

11:00 AM

3A.1, 3A.2, & 3A.3 Authors Corner

1:00 PM

Workshop - To be announced

2:45 PM

Keynote: Ventiva ICE Ionic Cooling Engine

4:05 PM

4A.1 ESD Air Discharges into Shielded Automotive RF Connectors

4:30 PM

4A.2 Radial Transmission Line Effects in Charged Device Model Events and Testing

4:55 PM

4A.3 Effect of Pulse Duration in Transient Latchup Events

5:20 PM

4A.4 Degradation of PN-Junction Devices Subjected to Multiple Surge Pulses

5:45 PM

4A.1, 4A.2, 4A.3, & 4A.4 Authors Corner

6:05 PM

Discussion Group - To be Announced

Wednesday, September 17

8:00 AM

Morning Welcome

8:10 AM

Keynote: Backside Interconnects for Future Advanced Nodes

9:40 AM

5A.1 Metal Electrothermal Model for Circuit Simulation

10:05 AM

5A.2 Empirical ESD Modeling of ESD Pass Gate Transistors

10:30 AM

5A.3 Corona Discharge to Touchscreen Modeling Using Nonlinear Time-dependent Corona Streamer Propagation Model in SPICE

11:15 AM

6A.1 ESD Power Clamp Using Variable Clamping Voltage for Enhanced ESD Robustness and Prevention of False Triggering in High Voltage Applications

11:40 AM

6A.2 Area-Efficient and Low-Leakage Design for GaN-on-Si Power-Rail ESD Clamp Circuit With D-Mode HEMT

12:05 PM

6A.1 & 6A.2 Authors Corner

1:10 PM
2:55 PM

7A.1 Transient Simulation of CDM Currents in a Multichip Module Based on Measurements and 3D FEM Simulations

3:20 PM

7A.2 ESD EDA Verification Evolution for Packages and Modules

3:45 PM

7A.3 Ultrafast Characterization of Gated and STI Diodes in Bulk FinFET and GAAFET Technologies

4:10 PM

7A.4 Charge Trapping Mechanism in Thick Oxide of HV LDMOS Under CDM Events

4:35 PM

7A.1, 7A.2, 7A.3, & 7A.4 Authors Corner