Agenda

IEC61000-4-2 describes the way how to qualify electronic systems with regards to ESD events.
Nevertheless there are details which are not defined. 
-    How is the gun variability taken into account?
-    How to deal with the poor reproducibility of an air discharge?
In the standard there is no word about the actual test strategy.
-    How to approach the qualification of a complex electronic application?
-    How to optimize a system where there are many influencing factors (components and system design)?
-    Is it all trial and error or are there ways to approach this more systematically?
-    How is the application tested after a test to see if it is functional?
If the system fails the tests: 
-    What kind of analysis is done to find the root cause and to optimize the application?
-    Hard fails vs soft fails: In which way the analysis is different?
-    Is this analysis done in-house or are the reasons to involve more parties such as component suppliers and what makes sense to share to enable an efficient collaboration?
In a perfect world, how would a perfect set up look like? Would there be Co-design to avoid failures and which information would be needed to be shared?

Over the past few years, ESD standard model development has gained momentum, with the Si2 Compact Modeling Coalition (CMC) releasing the ASM-ESD diode model and now working on a new ESD FET snapback model. ESD SPICE models are crucial for “first time right” ESD designs, especially in advanced CMOS technologies with continuously decreasing device failure levels and the need for high-speed IOs that don’t tolerate ESD “over design”. Standardized ESD models offer an opportunity for the industry to “speak a common modeling language”, for example, through their adoption in foundry PDKs. How do designers currently use ESD standard models? Are they easy to use? What are the most important model features? How can we lower the barriers for adopting standard ESD models? Please come and bring your questions and experience to this workshop!