Agenda

This paper presents a new current sensor, which incorporates two microstrip lines: one designed for charging the device under test (DUT) and the other facilitating precise discharges into a 33 GHz oscilloscope. Using a fully automated measurement setup with an incorporated pick and place tool, we aim to gather extensive statistical data across four distinct chiplet sizes. The study focuses on low pre-charge voltages between 1 V and 100 V to address current and future discharge target levels. It helps to establish the link between voltages and discharge currents for both ESD protection design and ESD process control.

Authors

Ellen Merkel, Heinrich Wolf, Leon Heiland, Fraunhofer EMFT

An automated Latch-up tester was catastrophically damaging a small number of units. Initially declared as a latch-up failure, root cause analysis found the damage to be caused by an excessive voltage pulse. The pulse was erroneously and intermittently delivered to biased pins in the idle time between signal pin tests.

Authors:

Scott Ward, James McGee, Texas Instruments;  Tom Meuse, Thermo Fisher Scientific

Visit with the authors of 1B.1 and 1B.2 to discuss their paper presentations in great detail.

Controlling electrostatic discharges in electronics, automotive, and process industries often relies on volume and surface resistance measurements. These methods overlook discharge power and energy distributions due to voltage dependence and breakdown characteristics. This study highlights these limitations and introduces methods to improve measurement accuracy, reliability, and safety.

Authors

Toni Viheriäkoski, Cascade Metrology Oy; Jean-Luc Houalla, Eurostat; Reinhold Gärtner, Infineon Technologies AG;
Wolfgang Stadler, Intel Deutschland GmbH; Pasi Tamminen, Danfoss Drives Oy

Corona discharge ionizers are widely used to eliminate static electricity. In general, the performance required is the static elimination speed and ion balance. In recent years, interest in the peak value of ion balance has increased as the ESD immunity of electronic devices have declined. In particular, it is expected to become a new requirement to suppress induced potential by AC electric field from the high-voltage section of AC type ionizers.

In this paper, induced charging phenomenon that occurs under the influence of AC electric fields emitted from discharge electrodes and main body of the ionizer, which is a prominent phenomenon in AC type ionizers, is investigated by installing a grid made of electrostatic dissipative material (surface resistance: E4 to E11 Ω) near the discharge electrodes and taking similar measures to the main body to reduce induced voltages and increasing decay time.

Ion balance including induction voltage was improved from ±65 V to ±15 V, and decay time was reduced to less than half that of the conventional product. In addition, compressed air was applied and measure not only induced charging but also ion pulsation flow was observed.

Authors

Shinichi Yamaguchi, Shishido Electrostatic, Ltd.

Visit with the authors of M1.1 and M1.2 to discuss their paper presentations in great detail.

Electrostatic Attraction plagues many sectors of industry. Industries such as semiconductor wafer fabrication, aerospace, medical device manufacturing, and others experience significant losses due to scrap, rework, and lost productivity due to electrostatic attraction. While the phenomenon is anecdotally well understood, limited resources are available for those who want to exercise some control over ESA. EOS/ESD Association, Inc. is the leading international source of electrical overstress (EOS) and electrostatic discharge (ESD) control. The Association recognizes that other sources and organizations (such as the Journal of Electrostatics and the Institute of Environmental Sciences & Technology) or specific industry-segment focus groups (such as SEMI) address individual aspects of this multidisciplinary problem. However, there is not a comprehensive approach to controlling ESA in many of the industry documents available. As a result of this industry need, a working group was formed in 2018 to develop a document (ESD TR28) which has recently been published. This talk will review the content of TR28, highlighting the key parts of the document and how it addresses the needs of various industries.

Material resistance recommendations to mitigate charged device model (CDM)-type risks in electronics are often overestimated due to insufficient evidence. Standard resistance tests fail to reflect actual CDM-like conditions involving higher resistances. This study shows that recommended resistance values can be significantly below 1 MΩ when addressing CDM-related concerns.

Authors

Toni Viheriäkoski, Cascade Metrology Oy; Pasi Seppälä, Premix Oy; Wolfgang Stadler, Intel Deutschland GmbH;
Friedrich zur Nieden, Lena Zeitlhoefler, Infineon Technologies AG; Pasi Tamminen, Danfoss Drives Oy

Charged plate monitors (CPMs) are used to evaluate ionizers. Due to the processing of very sensitive components, ionizer requirements are also changing. This work shows that today's CPMs are not suitable for all measurements of ionizers, and changes are required in standardization so that CPMs meet today's requirements.

Authors

Wolfgang Stadler, Arman Vassighi, Intel; Rainer Pfeifle, Wolfgang Warmbier GmbH & Co. KG

Visit with the authors of M1.3 and M1.4 to discuss their paper presentations in great detail.

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As the semiconductor industry advances toward increasingly complex systems, heterogeneous integration (HI) has emerged as a critical technology, combining multiple components—such as logic, memory, analog, RF, and photonics—into a single package. This integration approach presents significant challenges in managing electrostatic discharge (ESD), which can compromise reliability and yield if not properly addressed. This workshop provides an overview of ESD challenges unique to HI, including issues related to varying device sensitivities from traditional pins exposed outside of the package to internal die-to-die interfaces, and the increasing number of opportunities for ESD during the complex advanced packaging steps from wafer probe to final test. The session will delve into three core areas: ESD testing, highlighting emerging methodologies for multi-die and 3D stack configurations; ESD verification, focusing on simulation and design rule strategies tailored for heterogeneous systems; and ESD control, discussing best practices in manufacturing, handling, and packaging environments. Attendees will gain practical insights into industry standards, protection schemes, and verification approaches to ensure ESD robustness in next-generation semiconductor products.

A new SCR-LDMOS is investigated through 2D/3D TCAD simulations to obtain maximum holding voltage, minimum area and high ESD robustness. The effect of the additional floating-p region is studied. Reduced overvoltage and turn-on time are observed in the very-fast pulsed regime. Tunability of the holding voltage is demonstrated.

Authors

Giacomo Drudi, Susanna Reggiani, University of Bologna; Rajkumar Sankaralingam, Mariano Dissegna, Gianluca Boselli, Texas Instruments Inc.

An alternative conceptual approach for ESD on-chip protection comprising gate controlled NLMOS- SCR devices and enable drivers is proposed and experimentally validated. The new principle of clamp design allows operation in two different automatically selected modes. Protection mode features triggering voltage level significantly lower than maximum operation voltage of the protected pin, while in normal mode the triggering voltage is substantially higher. Reliable functionality of the circuit suitable for voltage domains from 14V to 85V is demonstrated.

Authors

Vladislav Vashchenko, Analog Devices, Inc; Andrei Shibkov, Angstrom Design Automation

The presentation covers challenges in scaling high-speed interconnect bandwidths, including; Single-ended signaling techniques and common design issues; State-of-the-art comparison and tradeoffs of organic package and interposer links; Methods of improving signal integrity; Clock forwarding techniques; PHY transceiver topology tradeoffs. The pad/ESD capacitance in high-speed links and a method for compensating for it is discussed.

Authors

Walker Turner, Nvidia

Visit with the authors of 2B.1, 2B.2, and 2B.3 to discuss their paper presentations in great detail.

An on-chip active probe that enables measurement of ESD transients at internal circuit nodes is demonstrated. The probe’s bandpass characteristics are targeted for CDM. The probe is used to capture transient voltage waveforms at internal nodes of three high-speed transmitters located on a packaged IC during 1-ns vf-TLP testing.

Authors

Matthew Drallmeier, Elyse Rosenbaum, University of Illinois at Urbana-Champaign

This paper introduces an on-chip ESD detection circuit and methodology for high current ESD discharges occurring to the back-side bulk silicon during wafer fabrication and assembly process. 

Authors

James Davis, Souvick Mitra, Ken Marr, Greg O’Sullivan, Kevin Werhane, Micron Technology

A peak current failure threshold miscorrelation was observed between CDM (~8.4A) testing and capacitively coupled (CC)-TLP (~11.5A) characterization of multi-GHz RF pins. Both field induced CDM and CC-TLP test methods also revealed a different failure mechanism and signature. The failure threshold of the multi-GHz RF pins appeared to be ultra-fast rise time (Tr~50ps) dependent.

Authors

Dolphin Abessolo-Bidzo, NXP Semiconductors; Johannes Weber, Heinrich Wolf, Fraunhofer EMFT

Visit with the authors of 3B.1, 3B.2, and 3B.3 to discuss their paper presentations in great detail.

This presentation explores the unique and severe hazards posed by electrostatic discharge (ESD) in explosive environments. We will delve into the fundamental mechanisms of ESD ignition in these atmospheres. 
This talk will outline specific mitigation strategies crucial for safe handling and manufacturing. This session will highlight key differences from standard ESD S20.20 controls, emphasizing the specialized approaches required to prevent catastrophic incidents involving explosives.

Details to be Announced

High reliability products are designed and built to operate consistently and without failure. Deployed in mission critical applications, they support aerospace, defense, medical, safety critical systems, and other industries. Manufacturing high reliability product must include a robust quality-controlled process, including a comprehensive ESD control plan. Electrostatic discharges during manufacturing may cause electrical failures of ESD sensitive products. These failures might be caught through normal testing processes prior to delivery, but some failures may not show up until after the product is deployed in the field (latent defects). 
 
So, what needs to happen when an element of the company's ESD control plan is missed, potentially leading to catastrophic or latent failure? If a person forgets to connect their ground cord or fails to use appropriate packaging, is it cause for automatic scrap, or is there a way to determine if and what risk was posed to the product? In this invited talk, Devin will share how his team dispositions non-conformances on high-reliability products and the benefit of overlapping layers of protection. 

Current ESD event detection tools often difficult to distinguish between EMI noise from production environment and genuine ESD events on products. This paper introduces a novel method using machine learning (ML) to accurately differentiate genuine EMI signal from noises emitted by assembly and test tools. This approach involves capturing comprehensive wave packet signals with a high-frequency data acquisition system and omnidirectional antennas, transforming these signals from the time domain to the frequency domain using Fourier transformation, and employing unsupervised deep learning techniques for classification. This method effectively isolates pure ESD signals from tool EMI noises. This advanced ESD detection system significantly enhances the accuracy and reliability of identifying valid ESD events in complex production environments, overcoming the limitations of existing detection methods.

Authors

Byung Hoon Moon, Greg O'Sullivan, Bong Andres, Siddhant Sharma, Hugo Chen, Ken Hau Chang, Micron

The antenna response to fast ESD events is analyzed in frequency and time domain. The characteristics of an antenna are studied using a Vector Network analyzer (VNA) and TLP. The results are used to analyze under which conditions an IC’s discharge in an ESD-critical process step can be detected. Through measurements and 3D simulations, the IC’s discharge current and risetime can be estimated.

Authors

Mohamed Chefai, Lena Zeitlhoefler, Friedrich zur Nieden, Infineon Technologies AG

Visit with the authors of M2.1 and M2.2 to discuss their paper presentations in great detail.