Saturday, September 13

8:30 AM
8:30 AM - 4:30 PM PDT

Introduction to On-Chip ESD Protection

This tutorial is designed to provide a comprehensive understanding of electrostatic discharge (ESD) events and its implications on semiconductor devices. The tutorial will delve into the fundamentals of ESD, including the physics behind the electrostatic build-up and discharge processes. Integrated circuits can get damaged by ESD events during manufacturing, testing or in assembly when they are handled by people or machines. IC layout engineers can influence the robustness of their circuits by applying guidelines and tricks. Participants will explore various ESD protection strategies and design methodologies used in modern integrated circuits (ICs). The material will cover ESD devices used from basic CMOS to advanced FinFET technologies. The session will cover key topics such as on-chip ESD protection device structures and layout considerations, Through a blend of theoretical knowledge and practical examples, the tutorial aims to equip attendees with the skills necessary to understand on-chip ESD protection schemes. This tutorial is ideal for IC engineers seeking to enhance their expertise in ESD protection for semiconductor devices.   

Learning Outcomes:

  • Fundamental understanding about Electrostatic Discharge (ESD): Gain a solid understanding of the principles of electrostatic discharge, including the causes and effects of ESD events in semiconductor devices
  • Introduction to on-chip ESD Protection Strategies: Learn about various ESD protection mechanisms and their integration into IC design, including diode, transistor, and SCR-based approaches.
  • Practical Case Studies: Analyze real-world examples to understand common challenges and best practices in ESD protection for different types of ICs.
  • Layout Considerations: Understand the critical layout considerations that impact the effectiveness of ESD protection schemes.
Olivier Marichal

Olivier Marichal

Chief Engineering
SOFICS

Olivier Marichal graduated from Katholieke Universiteit Leuven with a degree in Electrical Engineering in 2003 and has since dedicated his career to the field of Electrostatic Discharge (ESD) protection design, currently serving as Chief Engineering at Sofics. His journey with the company began shortly after graduation as an ESD engineer, and over the years, Olivier has worked on many projects, covering a broad range of technologies from High Voltage BCD to the latest nanometer Finfet and GAAFet processes. His professional focus is on continuously adding value to customers through his work, delivering state-of-the-art ESD solutions for the ever evolving landscape of semiconductor applications.  Olivier has (co-)authored several papers on ESD and contributed as an inventor on many patents. In addition to his technical contributions, Olivier is dedicated to sharing his knowledge and insights. He has conducted several tutorials on on-chip ESD protection design for industry professionals around the world.

8:30 AM - 4:30 PM PDT

Sunday, September 14

8:30 AM
8:30 AM - 12:00 PM PDT

Introduction to Characterization of On-Chip ESD Protection

This tutorial is designed to provide a comprehensive understanding of electrostatic discharge (ESD) events and its implications on semiconductor devices. The tutorial will delve into the fundamentals of ESD, including the physics behind the electrostatic build-up and discharge processes. Integrated circuits can get damaged by ESD events during manufacturing, testing or in assembly when they are handled by people or machines. IC layout engineers can influence the robustness of their circuits by applying guidelines and tricks. Participants will explore various ESD protection strategies and design methodologies used in modern integrated circuits (ICs). The material will cover ESD devices used from basic CMOS to advanced FinFET technologies. The session will cover key topics such as on-chip ESD protection device structures and layout considerations, Through a blend of theoretical knowledge and practical examples, the tutorial aims to equip attendees with the skills necessary to understand on-chip ESD protection schemes. This tutorial is ideal for IC engineers seeking to enhance their expertise in ESD protection for semiconductor devices.   

Learning Outcomes:

  • Fundamental understanding about Electrostatic Discharge (ESD): Gain a solid understanding of the principles of electrostatic discharge, including the causes and effects of ESD events in semiconductor devices
  • Introduction to on-chip ESD Protection Strategies: Learn about various ESD protection mechanisms and their integration into IC design, including diode, transistor, and SCR-based approaches.
  • Practical Case Studies: Analyze real-world examples to understand common challenges and best practices in ESD protection for different types of ICs.
  • Layout Considerations: Understand the critical layout considerations that impact the effectiveness of ESD protection schemes.
Wim Vanhouteghem

Wim Vanhouteghem

Senior ESD Design Engineer
SOFICS

Wim Vanhouteghem is a Senior ESD Design Engineer and the head of the measurement lab at Sofics. A 2007 graduate of KHBO - now part of the Catholic University of Leuven, Wim joined Sofics immediately after completing his studies. His work primarily focuses on ESD protection in semiconductor technologies, ranging from high voltage BCD to FinFETs.  Wim has plenty of experience in implementing ESD protection and conducting ESD measurements. He contributed to the SEED concept and has worked on system-level ESD measurements on bare dies. 

8:30 AM - 12:00 PM PDT
1:00 PM
1:00 PM - 4:30 PM PDT

Beyond Standard TLP - Better ESD Design With the Right Data

This tutorial shows what data you actually need for a good ESD design and what you should get or request from the foundry. It is an interesting starting point for many companies. 

Efraim Aharoni

Efraim Aharoni

Senior Principal Engineer
Tower Semiconductor

Efraim Aharoni received the M.Sc. and Ph.D degrees in Physics  in 1989 and 1994 from the Technion, Israel Institute of Technology. His research in the Technion was focused on High Temperature Superconducting devices. In 1993 he joined Tower Semiconductor. Efraim worked in Tower in a variety of fields, in both engineering and management, in development as well as production. Amongst his engineering roles: process, device, yield, director R&D CMOS, and director of reliability. In the past 15 years, he has led the ESD and Latch-Up activities in the company as a senior principal engineer. This involves the development of new ESD devices and protection concepts, creating libraries of ESD devices in PDK, development of a unique concept of ‘empirical ESD modeling (for simulation of circuits containing snap-back based devices), PERC, and customer support. He works closely with the Tower design center, device engineers, PDK group, customers, and production lines, in Tower Semiconductor sites worldwide. Efraim served in the technical committees of IEW and EOS/ESD symposium, is a co-chair of WG22, and a member in the Industry Council of ESD Standards. In addition, he serves as the head of the Electrical Engineering department in the Kinneret College on the sea of Galilee and lectures on a variety of courses.

1:00 PM - 4:30 PM PDT