Monday, October 2

8:00 AM

Welcome - Track 1

8:05 AM

Invited Talk: Transmission Line Pulse Testing - 5 Years in Review

8:35 AM

1A.1 Sensor Gap TLP: Expanding Time Resolution and Pulse Duration Beyond Conventional Values of Standard and Very Fast Transmission Line Pulsing

9:00 AM

1A.2 ESD Stress Data Analysis with Machine Learning: A Case Study

9:25 AM

Authors Corner for 1A.1 & 1A.2

9:55 AM

1A.3 Novel ESD Characterization Method for Bipolar Devices Using a Combined TLP System with Dynamic Base Bias

10:20 AM

1A.4 Impact of a Deep Junction Depth Coupled with a Short Channel Length on the ESD Robustness of a Grounded Gate nMOS Clamp

10:45 AM

Authors Corner for 1A.3 & 1A.4

11:15 AM

1A.5 Discharge Waveforms of Emulated Die-to-Die ESD Discharges

11:40 AM

1A.6 Voltage to Current Correlation for CDM Testing

12:05 PM

1A.7 Study of Frequency Response of CDM Setup

12:30 PM

Authors Corner 1A.5, 1A.6, & 1A.7

1:30 PM

Clearing the Air (Presentation and Interactive Workshop)

3:30 PM

Invited Paper: Modeling an ESD Gun Discharge to a USB Cable

3:55 PM

Invited Paper: Measurement of Current Waveform Due to Different Load of ESD Gun, TLP-HMM, and CR-HMM

4:20 PM

Break in Track 1 (Exhibit Hall C) sessions

4:50 PM

1B.1 IEC ESD Co-Design Methodology for On-Chip Protection at High Voltage Transceivers

5:15 PM

1B.2 On the Safety Distance to Avoid Transient Latch-up During System Level ESD Stress

5:40 PM

Authors Corner 1B.1 & 1B.2

Tuesday, October 3

10:35 AM

Invited Paper: CAD-Based ESD Protection Design Methodologies

11:55 AM

Break (Exhibit Hall C)

12:05 PM

3A.1 Impact of Backside Power Delivery Network with Buried Power Rails on Latch-up Immunity in DTCO/STCO

12:30 PM

3A.2 High thermal conductive Graphene-based Composites and its Controllable ESD Application on Device Packaging

12:55 PM

Authors Corner 3A.1 & 3A.2

Wednesday, October 4

9:55 AM

5A.3 A Hybrid Finite Difference Model for Open Base Transistors with Kirk Effect

10:20 AM

5A.4 Physics-Based Compact Model of N-Well ESD Diodes

10:45 AM

5A.5 Effective ESD Design Through PERC Programming

11:10 AM

Authors Corner 5A.3, 5A.4, & 5A.5

11:55 AM

5A.1 A Combined Model for Transient and Self-Heating of Snapback Type ESD Protection Devices

12:20 PM

5A.2 A Versatile Behavioral Snapback ESD Model Incorporating Transient Effects and Failure Detection

12:35 PM

Authors Corner 5A.1 & 5A.2

3:35 PM

Invited Talk: Silicon Photonics: Are we there yet?

4:25 PM

4A.1 Distributed Protection for High-Speed Wireline Receivers

4:50 PM

4A.2 Consideration based on ESD applied waveform in High-Speed IF using T-Coil (RCJ Best Paper)

5:15 PM

4A.3 Fast Transient ESD Protection at RF Pins

5:40 PM

Authors Corner 4A.1, 4A.2, & 4A.3