Tuesday, October 3

10:35 AM
10:35 AM - 11:25 AM PDT

Invited Paper: CAD-Based ESD Protection Design Methodologies

Author: Albert Wang, University of California - Riverside

 

Now more than ever, CAD-based design methodologies become essential to achieving optimization and validation of on-chip ESD protection design, particularly for complex ICs in emerging technologies, including 3D hetero-integrated chips. This talk reviews some useful ESD protection design methodologies, including TCAD-based mixed-mode ESD simulation-design method, ECAD-based full-chip ESD protection design techniques, CAD-enabled ESD-IC co-design considerations, and new CAD algorithms enabling full-chip ESD protection physical design verification. Outlook for ESD protection for emerging technologies and 3D chiplets-based heterogeneous microsystem chips will be discussed. Practical ESD protection design examples will be given.

Albert Wang

Albert Wang

University of California-Riverside

Albert Wang received a BSEE degree from Tsinghua University and a Ph.D. EE degree from the State University of New York at Buffalo. He was a Silicon Valley IC designer before joining academia. Currently, he is a Professor of Electrical and Computer Engineering at the University of California, Riverside, where he is Director of the Laboratory for Integrated Circuits and Systems, and Director of the University of California Center for Ubiquitous Communications by Light. He served as a Program Director of the National Science Foundation (2019-2021). His research covers Analog/Mixed-Signal/RF ICs, Integrated Design-for-Reliability, 3D Heterogeneous Integration, Emerging Nano Devices and Circuits, and LED-based Visible Light Communications. He published 2 books and 320+ papers and holds 16 US patents. His editorial board services include IEEE Electron Device Letters, IEEE Transactions on Circuits and Systems I, IEEE Transactions on Circuits and Systems II, IEEE Journal of Solid-State Circuits, IEEE Transactions on Electron Devices, IEEE Journal of Electron Devices Society, and IEEE Transactions on Device and Materials Reliability. He is/was an IEEE Distinguished Lecturer for the IEEE Electron Devices Society, IEEE Solid-State Circuits Society, and IEEE Circuits and Systems Society. He was President of the IEEE Electron Devices Society (2014-2015). His other professional services include SIA International Technology Roadmap for Semiconductor (ITRS) Committee, IEEE Heterogeneous Integration Roadmap (HIR) Committee, IEEE 5G Initiative Committee, IEEE Fellow Committee, IEEE IoT Technical Community Steering Committee and IEEE Smart Lighting Project Roadmap Committee. He was General Chair for IEEE RFIC Symposium (2016) and IEEE EDTM (2021). Wang is a recipient of the IEEE J. J. Ebers Award (2022). Wang is a Fellow of the National Academy of Inventors and a Fellow of IEEE.

Invited Paper: CAD-Based ESD Protection Design Methodologies

12:05 PM
12:05 PM - 12:30 PM PDT

3A.1 Impact of Backside Power Delivery Network with Buried Power Rails on Latch-up Immunity in DTCO/STCO

Authors: Kateryna Serbulova, Guido Groeseneken, KU Leuven, imec; Shih-Hung Chen, Geert Hellings, Anabela Veloso, Anne Jourdain, Jo De Boeck, Eugenio Dentoni Litta, Naoto Horiguchi, imec

 

In this work, the impact of buried power rail (BPR) on latch-up (LU) immunity is discussed. Measurements and simulation results indicate differences in the current gain product with different BPR bias variations. The inappropriately applied voltage to the BPR lines induces unexpected LU risk, which is investigated.

Kateryna Serbulova

Kateryna Serbulova

KU Leuven, imec

Kateryna Serbulova is a Ph.D. student in the Department of Electrical Engineering at KU Leuven and at imec. She is interested in issues concerning latch-up prevention techniques. Kateryna Serbulova studied micro- and nanotechnology and obtained her B.S. and M.S. at the National Technical University of Ukraine "Igor Sikorsky Kyiv Polytechnic Institute ", Ukraine, in June 2019. After spending a term as an internship student at imec, she joined the Department of Electrical Engineering at KU Leuven and imec in October 2019. Currently, she serves as a TPC member for EOS/ESD Symposium.

3A.1 Impact of Backside Power Delivery Network with Buried Power Rails on Latch-up Immunity in DTCO/STCO

12:30 PM
12:30 PM - 12:55 PM PDT

3A.2 High thermal conductive Graphene-based Composites and its Controllable ESD Application on Device Packaging

Authors: Rong-Teng Lin, Bi-Xian Wu, Yun-Hong Yang, Teng-Chin Hsu, Chia-Lien Chao, Yu-Chiao Chang, Chiao-Jung Su, Chien-Hao Liu, Tzu-Hsuan Chang, National Taiwan University; Jam-Wem Lee, Kuo-Ji Chen, Wun-Jie Lin, TSMC

 

A novel ESD protection technique was achieved through packaging material with uniformly dispersed graphene nanosheets. The ESD protection can be self-activated in nanoseconds with manageable Vth within a few volts. The application of packaging material demonstrates that high thermal conductivity, EMI protection capability, and ESD protection can be achieved simultaneously.

Rong-Teng Lin

Rong-Teng Lin

National Taiwan University

Rong-Teng Lin received his M.S. from the Graduate School of Electronics Engineering at the National Taiwan University in 2022.

3A.2 High thermal conductive Graphene-based Composites and its Controllable ESD Application on Device Packaging

12:55 PM
12:55 PM - 1:15 PM PDT

Authors Corner 3A.1 & 3A.2

Rong-Teng Lin

Rong-Teng Lin

National Taiwan University

Rong-Teng Lin received his M.S. from the Graduate School of Electronics Engineering at the National Taiwan University in 2022.

Kateryna Serbulova

Kateryna Serbulova

KU Leuven, imec

Kateryna Serbulova is a Ph.D. student in the Department of Electrical Engineering at KU Leuven and at imec. She is interested in issues concerning latch-up prevention techniques. Kateryna Serbulova studied micro- and nanotechnology and obtained her B.S. and M.S. at the National Technical University of Ukraine "Igor Sikorsky Kyiv Polytechnic Institute ", Ukraine, in June 2019. After spending a term as an internship student at imec, she joined the Department of Electrical Engineering at KU Leuven and imec in October 2019. Currently, she serves as a TPC member for EOS/ESD Symposium.

Authors Corner 3A.1 & 3A.2