Agenda

System-level ESD requirements (like IEC 61000-4-2 and ISO 10605) are intended for electronic systems and not for individual integrated circuits (ICs)— yet it is becoming increasingly common to see specifications of system-level ESD performance at the IC-level.  In fact, additional standards (like J-2962-x and IEC-62228-x) have been created to facilitate such testing, specifically in the automotive market.  While system-level performance at the IC-level may be desirous, the relevance of this performance is unclear.  This is especially true for air-discharge testing, which is already known to present significant repeatability challenges.  This is further complicated by the fact that there is no expected current waveform for the air-discharge event.  Many different current waveforms are possible and none of them has been deemed the correct one.

While some of the issues surrounding air-discharge have been documented, this presentation will take a deeper look at known issues, identify previously unreported issues, and ultimately provide a comprehensive documentation of the challenges involved in performing air-discharge testing on an IC.  Ultimately this presentation will make the case that insufficient rigor is present in the standard test methods to justify specifying air-discharge requirements at the IC level.

Moderator: Michael Khazhinsky, Silicon Laboratories

The verification of ESD protection in modern integrated circuits is a difficult challenge. There are several factors, including increasing design and process complexity, higher pin counts, use of mixed voltages, power management, etc., that make ESD analysis especially challenging.

EDA checking/verification tools designed for effective ESD protection are getting used more and more. This includes schematic and layout-based checks, including current density (CD), point-to-point (P2P) resistance analyses, simulation-based methods, like SPICE compact model simulations, and Technology CAD (TCAD). Other EDA checks include verification on the package and system levels. All these checks are part of the ESD TR18.0-01 - ESD Association Technical Report for ESD Electronic Design Automation Checks. This report was first published in 2011 and is now being revised.

Come meet the authors of the technical report in this World Café style workshop. Share what your concerns are in the field to make sure they are addressed in the upcoming revision of the Technical Report. Bring your experiences and thoughts/innovations.

Hand tools are commonly used during the assembly of ESD-sensitive products, but are commonly overlooked as a potential ESD risk. This workshop reviews existing measurement techniques and how they can help you understand the ESD risks associated with hand tools.

Details forthcoming

Details Forthcoming...

Next to the ESD target level, the ESDA technology roadmap presents tthe current technical challenges and an outlook for the coming years in ESD and latch-up. In this workshop, the Advanced Topics team presents to you first what the next 2023 edition will look like. This is followed by an open discussion where we want to collect your feedback and input. Our goal is that the ESDA technology roadmap becomes a document of the worldwide ESD and latch-up community. It is our aim that it supports and guides the daily work of ESD and latchup experts in industry and academia.

In this workshop, we will discuss the elements of an effective ESD design infrastructure provided by foundries.  The major areas of an ESD design infrastructure include an ESD protection device library, compact models for ESD protection devices, measurement data for ESD protection and victim devices, documentation, and ESD verification tools.  To provide multiple perspectives, this workshop will have moderators representing foundry customers, foundries, and Working Group 22.  These perspectives will allow us to prioritize the most important components of an ESD design infrastructure from the customer's point of view while evaluating the feasibility of their implementation from the foundry's point of view.

Moderator: Ann Concannon, TI, and Symposium General chair

As technologies advance and scale, standards are required to ensure performance conformity and safety of new products and processes, as is evident in the semiconductor industry and the mission of the ESDA. Standards form the backbone of this Association,  involving many 1000s of volunteer hours working on committees to update, publish, and ultimately use the standards daily. Join in the discussion with a panel of industry professionals who will discuss the importance of the ESDA standards, the process of creating standards, misunderstood standards, and the work not yet done.

Distinguished panelists include

• Brett Carn, Intel and Former EOS/ESD Association, Inc. Standards Business Unit Manager
• Julie Van Campen, NASA,  the James Webb Space Telescope Lead Systems Engineer for the Integrated Science Instrument Module and the Deputy Commissioning Manager
• Keith Peterson, Missile Defense Agency