Monday, September 19

9:00 AM

Tutorial - Basics of Latch-up Testing

10:15 AM
10:35 AM

2A.3 - A Comparison between Low Impedance Contact CDM and Field Induced CDM: Measurement and Simulation

11:00 AM

2A.2 - Electrostatics of the Resistor-Blocked CDM Probe Pulse

11:25 AM
11:35 AM

2A.1 - Limitation of CDM Testing for Small Devices

12:00 PM
1:00 PM

Topic in Review - Full Chip and IP Level CDM Simulation and Verification

1:40 PM
2:00 PM

Invited Talk - Does Silicon Photonics Need any ESD Protection?

2:50 PM
3:10 PM

Seminar - ESD Protection for RF Switches

3:50 PM

Tuesday, September 20

9:50 AM
10:20 AM
10:30 AM

Topic in Review - Recent Challenges and Improvements in Latch-up Prevention for Advanced CMOS Technologies

11:10 AM
11:30 AM

2B.1 - Hidden Threats During Automated Latch-up Testing

11:55 AM

2B.2 - CMOS Latch-up Improvement: Embedded Active Collector in FinFET Technology

12:20 PM
1:20 PM

Exhibitor Showcase - Thermo Fisher Scientific

1:30 PM

Invited Talk - Release of JEDEC JESD78 Rev F Latch-up Standard and the Effects the Changes May Have on Your Device Testing

2:20 PM
3:00 PM

2B.3 - The HBM Tester Parasitics Problem

3:25 PM

2B.4 - Total Tester/PKG/Chip Circuit-Modeling Methodology for Predicting Highly Precise CDM Breakdown Voltage (RCJ Invited Paper)

3:50 PM

Invited Paper - Enabling Active Backside Technology for ESD and LU Reliability in DTCO/STCO (from the VLSI Conference)

4:15 PM

Authors Corner for 2B.3, 2B.4, & Invited Paper (NO LIVESTREAM)

Wednesday, September 21

8:00 AM

Workshop - Reduced CDM Targets for Ultra-High-Speed Interfaces (NO LIVESTREAM)

9:15 AM
10:00 AM

Showcase - EOS/ESD Association, Inc. Standards Business Unit Activities

10:10 AM

Invited Talk - ESD in 2.5D/3D Bonding Technologies

11:00 AM
11:45 AM

Seminar - Lifetime and Reliability Requirements in Automotive Electronics – Status and Challenges in 2022

12:25 PM
1:25 PM

4A.1 - Analysis of Input Receiver Transistors Behavior During a CDM Event

1:50 PM

4A.2 - Low-Capacitance, High-CDM ESD Protection Design with FEOL and BEOL Co-Optimization in 4nm Bulk FinFET Technology

2:15 PM
2:25 PM

4A.3 - Advanced CDM Simulation Methodology for High-Speed Interface Design

2:50 PM

Authors Corner for 4A.1 & 4A.3 (NO LIVESTREAM)

3:20 PM

Invited Talk - RF Front End High Performance Technologies and Trends

4:10 PM

Thursday, September 22

8:00 AM

Workshop - System-Level Tests of ICs - Do we have too many tests? (NO LIVESTREAM)

9:15 AM
9:35 AM

Invited Talk - Low Quiescent Current (IQ): Extending Battery Life Without Compromise

10:45 AM

Invited Talk - Think Nontraditionally for Future ESD Protection