Monday, September 19

9:00 AM

Tutorial - Basics of Latch-up Testing

10:35 AM

2A.3 - A Comparison between Low Impedance Contact CDM and Field Induced CDM: Measurement and Simulation

11:00 AM

2A.2 - Electrostatics of the Resistor-Blocked CDM Probe Pulse

11:35 AM

2A.1 - Limitation of CDM Testing for Small Devices

12:00 PM

Tuesday, September 20

10:30 AM

Topic in Review - Recent Challenges and Improvements in Latch-up Prevention for Advanced CMOS Technologies

11:30 AM

2B.1 - Hidden Threats During Automated Latch-up Testing

11:55 AM

2B.2 - CMOS Latch-up Improvement: Embedded Active Collector in FinFET Technology

12:20 PM
1:30 PM

Invited Talk - Release of JEDEC JESD78 Rev F Latch-up Standard and the Effects the Changes May Have on Your Device Testing

3:00 PM

2B.3 - The HBM Tester Parasitics Problem

3:25 PM

2B.4 - Total Tester/PKG/Chip Circuit-Modeling Methodology for Predicting Highly Precise CDM Breakdown Voltage (RCJ Invited Paper)

3:50 PM

Invited Paper - Enabling Active Backside Technology for ESD and LU Reliability in DTCO/STCO (from the VLSI Conference)

4:15 PM

Authors Corner for 2B.3, 2B.4, & Invited Paper (NO LIVESTREAM)

Thursday, September 22

8:00 AM

Workshop - CDM Testing for Bare Die – How are Companies Collecting Data? (NO LIVESTREAM)

9:35 AM

Invited Talk - ESD Handling and Control for the Circuit Designer: How Handling Requirements Relate to Device Robustness

10:40 AM

Invited Talk - A Look at CDM Target Levels and Implications for Future Design and Testing of Ultra-High-Performance I/O

12:10 PM

2C.2 - Tracing & Debugging of ESD Failures in a Module Assembly Line

12:40 PM